Cypress 37000 CPLD manual Input Macrocell, Timing Model

Page 6

Ultra37000 CPLD Family

FROM CLOCK POLARITY MUXES

INPUT PIN

 

 

 

 

 

0

 

 

 

 

 

 

1

O

 

 

 

 

 

2

 

D

 

D

 

 

0

Q

Q

3

 

1

O

 

 

 

 

 

 

 

 

2

 

 

 

 

C12 C13

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

C10 C11

 

 

 

 

 

 

 

D

Q

 

 

 

 

 

LE

 

 

 

 

 

Figure 3. Input Macrocell

TO PIM

FROM CLOCK POLARITY INPUT CLOCK PINS

 

 

 

 

 

 

0

O

 

TO CLOCK MUX ON

 

 

 

 

 

 

 

1

 

ALL INPUT MACROCELLS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INPUT/CLOCK PIN

 

 

 

 

 

C12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

O

 

 

 

 

 

 

 

 

 

1

TO CLOCK MUX

 

 

 

 

 

 

 

 

 

 

IN EACH

 

 

 

 

 

 

 

 

 

 

LOGIC BLOCK

 

 

 

 

 

 

 

0

 

C13, C14, C15

OR C16

 

 

 

 

 

 

 

1

O

TO PIM

 

 

 

 

 

 

 

 

2

CLOCK POLARITY MUX

 

 

D

 

D

 

 

 

 

0

 

Q

Q

 

3

 

 

ONE PER LOGIC BLOCK

 

 

 

 

 

 

1

O

 

 

 

 

 

 

 

 

FOR EACH CLOCK INPUT

2

 

 

 

 

 

C10C11

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C8 C9

D

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LE

 

 

 

 

 

 

 

 

Figure 4. Input/Clock Macrocell

Clocking

Each I/O and buried macrocell has access to four synchronous clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchronous product term clock PTCLK. Each input macrocell has access to all four synchronous clocks.

Dedicated Inputs/Clocks

Five pins on each member of the Ultra37000 family are desig- nated as input-only. There are two types of dedicated inputs on Ultra37000 devices: input pins and input/clock pins. Figure 3 illustrates the architecture for input pins. Four input options are available for the user: combinatorial, registered, double-registered, or latched. If a registered or latched option is selected, any one of the input clocks can be selected for control.

Figure 4 illustrates the architecture for the input/clock pins. Like the input pins, input/clock pins can be combinatorial, registered, double-registered, or latched. In addition, these pins feed the clocking structures throughout the device. The clock path at the input has user-configurable polarity.

Product Term Clocking

In addition to the four synchronous clocks, the Ultra37000 family also has a product term clock for asynchronous clocking. Each logic block has an independent product term clock which is available to all 16 macrocells. Each product term clock also supports user configurable polarity selection.

Timing Model

One of the most important features of the Ultra37000 family is the simplicity of its timing. All delays are worst case and system performance is unaffected by the features used. Figure 5 illustrates the true timing model for the 167-MHz devices in high speed mode. For combinatorial paths, any input to any output incurs a 6.5-ns worst-case delay regardless of the amount of logic used. For synchronous systems, the input set-up time to the output macrocells for any input is 3.5 ns and the clock to output time is also 4.0 ns. These measure- ments are for any output and synchronous clock, regardless of the logic used.

The Ultra37000 features:

No fanout delays

No expander delays

No dedicated vs. I/O pin delays

No additional delay through PIM

No penalty for using 0–16 product terms

No added delay for steering product terms

No added delay for sharing product terms

No routing delays

No output bypass delays

The simple timing model of the Ultra37000 family eliminates unexpected performance penalties.

Document #: 38-03007 Rev. *E

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Contents Ultra37000V 3.3V Devices FeaturesUltra37000 5.0V Devices Cypress Semiconductor CorporationSelection Guide Architecture Overview of Ultra37000 Family Programmable Interconnect MatrixLogic Block Product Term Allocator Ultra37000 MacrocellO and Buried Macrocells Input Macrocell Timing ModelDevelopment Software Support Jtag and PCI StandardsThird-Party Programmers Logic Block Diagrams CY37032/CY37032VCY37064/CY37064VInput CY37128/CY37128V CY37192/CY37192VLogic Block Diagrams CY37256/CY37256VCY37384/CY37384V TMSCY37512/CY37512V Range 0V Device Characteristics Maximum RatingsOperating Range2 Output ConditionInductance5 Endurance Characteristics53V Device Characteristics Maximum Ratings Capacitance5AC Characteristics Switching Characteristics Over the Operating Range Parameter Description Unit Product Term Clocking Parameters Pipelined Mode ParametersReset/Preset Parameters User Option ParametersProduct Term Reset/PresetSynchronous Operating Frequency ParametersJtag Timing Switching WaveformsUser Option Combinatorial OutputLatched Output Registered Input Clock to ClockLatched Input Output Enable/Disable Asynchronous ResetAsynchronous Preset Latched Input and OutputPower Consumption Typical 5.0V Power Consumption CY37032CY37064 Typical 5.0V Power Consumption CY37128 CY37192Typical 5.0V Power Consumption CY37256 CY37384Typical 5.0V Power Consumption CY37512 Typical 3.3V Power Consumption CY37032VTypical 3.3V Power Consumption CY37064V CY37128VTypical 3.3V Power Consumption CY37192V CY37256VTypical 3.3V Power Consumption CY37384V CY37512VPin Configurations20 Pin Tqfp A44 Top ViewPin Plcc J67 / Clcc Y67 Top View Ball Fine-Pitch BGA BA50 Top View Lead Plcc J83 / Clcc Y84 Top ViewLead Tqfp A100 Top View Ball Fine-Pitch BGA BB100 for CY37064V Top View Ball Fine-Pitch BGA BB100 for CY37128V Top ViewCLK3/I4 GND Lead Tqfp A160 for CY37192V Top View TDO I/OLead Pqfp N208 / Cqfp U208 Top View I/O I/O I/O I/O I/O I/O I/O I/OBall Pbga BG292 Top View Ball Fine-Pitch BGA BB256 Top View Lead Pbga BG388 Top View Ball Fine-Pitch BGA BB400 Top View Ordering Information 0V Ordering InformationLead Plastic Leaded Chip Carrier CY37064P84-154JC CY37128P84-167JC Lead Plastic Quad Flat Pack CY37256P256-154BGC 3V Ordering Information BB100 Lead Plastic Quad Flat Pack CY37256VP256-100BGC Package Diagrams Lead Lead Pb-Free Thin Plastic Quad Flat Pack A44Lead Lead Pb-Free Plastic Leaded Chip Carrier J67 Lead Ceramic Leaded Chip Carrier Y67 Ball 7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch Thin BGA BA48D Lead Lead Pb-Free Plastic Leaded Chip Carrier J83Lead Ceramic Leaded Chip Carrier Y84 Lead Lead Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85049-*B Lead Ceramic Quad Flatpack Cavity Up U162 Detail aLead Plastic Quad Flatpack N208 Lead Ceramic Quad Flatpack Cavity Up U208 Ball Fbga 17 x 17 mm BB256 Bottom ViewBall Plastic Ball Grid Array Pbga 27 x 27 x 2.33 mm BG292 Ball Plastic Ball Grid Array Pbga 35 x 35 x 2.33 mm BG388 Ball Fbga 21 x 21 x 1.4 mm BB400 Addendum 3V Operating Range Commercial3V ± Issue Orig. Description of Change Date Document History