Cypress 37000 CPLD manual Development Software Support, Jtag and PCI Standards

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Ultra37000 CPLD Family

 

 

COMBINATORIAL SIGNAL

 

 

 

 

 

 

 

 

 

tPD = 6.5 ns

 

 

INPUT

OUTPUT

 

 

REGISTERED SIGNAL

 

 

 

tS = 3.5 ns

 

 

 

tCO = 4.5 ns

 

 

 

 

 

D,T,L O

 

 

 

 

 

 

 

 

 

INPUT

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLOCK

Figure 5. Timing Model for CY37128

resources for pinout flexibility, and a simple timing model for consistent system performance.

Development Software Support

Warp

Warp is a state-of-the-art compiler and complete CPLD design tool. For design entry, Warp provides an IEEE-STD-1076/1164 VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a graphical finite state machine editor. It provides optimized synthesis and fitting by replacing basic circuits with ones pre-optimized for the target device, by implementing logic in unused memory and by perfect communication between fitting and synthesis. To facilitate design and debugging, Warp provides graphical timing simulation and analysis.

JTAG and PCI Standards

PCI Compliance

5V operation of the Ultra37000 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The 3.3V products meet all PCI requirements except for the output 3.3V clamp, which is in direct conflict with 5V tolerance. The Ultra37000 family’s simple and predictable timing model ensures compliance with the PCI AC specifica- tions independent of the design.

IEEE 1149.1-compliant JTAG

The Ultra37000 family has an IEEE 1149.1 JTAG interface for both Boundary Scan and ISR.

Boundary Scan

The Ultra37000 family supports Bypass, Sample/Preload, Extest, Idcode, and Usercode boundary scan instructions. The JTAG interface is shown in Figure 6.

Instruction Register

Warp Professional™

Warp Professional contains several additional features. It provides an extra method of design entry with its graphical block diagram editor. It allows up to 5 ms timing simulation instead of only 2 ms. It allows comparison of waveforms before and after design changes.

Warp Enterprise™

Warp Enterprise provides even more features. It provides unlimited timing simulation and source-level behavioral simulation as well as a debugger. It has the ability to generate graphical HDL blocks from HDL text. It can even generate testbenches.

Warp is available for PC and UNIX platforms. Some features are not available in the UNIX version. For further information see the Warp for PC, Warp for UNIX, Warp Professional and Warp Enterprise data sheets on Cypress’s web site (www.cypress.com).

Third-Party Software

TDI

TMS

TCK

JTAG

TAP

CONTROLLER

Bypass Reg.

Boundary Scan

idcode

Usercode

TDO

Although Warp is a complete CPLD development tool on its own, it interfaces with nearly every third party EDA tool. All major third-party software vendors provide support for the Ultra37000 family of devices. Refer to the third-party software data sheet or contact your local sales office for a list of currently supported third-party vendors.

Programming

There are four programming options available for Ultra37000 devices. The first method is to use a PC with the 37000 UltraISR programming cable and software. With this method, the ISR pins of the Ultra37000 devices are routed to a

ISR Prog.

Data Registers

Figure 6. JTAG Interface

In-System Reprogramming (ISR)

In-System Reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins. The Ultra37000 family implements ISR by providing a JTAG compliant interface for on-board programming, robust routing

connector at the edge of the printed circuit board. The 37000 UltraISR programming cable is then connected between the parallel port of the PC and this connector. A simple configu- ration file instructs the ISR software of the programming operations to be performed on each of the Ultra37000 devices in the system. The ISR software then automatically completes all of the necessary data manipulations required to accomplish the programming, reading, verifying, and other ISR functions. For more information on the Cypress ISR Interface, see the ISR Programming Kit data sheet (CY3700i).

The second method for programming Ultra37000 devices is on automatic test equipment (ATE). This is accomplished through a file created by the ISR software. Check the Cypress website for the latest ISR software download information.

Document #: 38-03007 Rev. *E

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Contents Cypress Semiconductor Corporation FeaturesUltra37000 5.0V Devices Ultra37000V 3.3V DevicesSelection Guide Programmable Interconnect Matrix Architecture Overview of Ultra37000 FamilyLogic Block Ultra37000 Macrocell Product Term AllocatorO and Buried Macrocells Timing Model Input MacrocellJtag and PCI Standards Development Software SupportThird-Party Programmers CY37032/CY37032V Logic Block DiagramsCY37064/CY37064VInput CY37192/CY37192V CY37128/CY37128VCY37256/CY37256V Logic Block DiagramsTMS CY37384/CY37384VCY37512/CY37512V Output Condition 0V Device Characteristics Maximum RatingsOperating Range2 RangeCapacitance5 Endurance Characteristics53V Device Characteristics Maximum Ratings Inductance5AC Characteristics Switching Characteristics Over the Operating Range User Option Parameters Pipelined Mode ParametersReset/Preset Parameters Parameter Description Unit Product Term Clocking ParametersOperating Frequency Parameters Reset/PresetSynchronous Product TermCombinatorial Output Switching WaveformsUser Option Jtag TimingLatched Output Clock to Clock Registered InputLatched Input Latched Input and Output Asynchronous ResetAsynchronous Preset Output Enable/DisableTypical 5.0V Power Consumption CY37032 Power ConsumptionCY37064 CY37192 Typical 5.0V Power Consumption CY37128CY37384 Typical 5.0V Power Consumption CY37256Typical 3.3V Power Consumption CY37032V Typical 5.0V Power Consumption CY37512CY37128V Typical 3.3V Power Consumption CY37064VCY37256V Typical 3.3V Power Consumption CY37192VCY37512V Typical 3.3V Power Consumption CY37384VPin Tqfp A44 Top View Pin Configurations20Pin Plcc J67 / Clcc Y67 Top View Lead Plcc J83 / Clcc Y84 Top View Ball Fine-Pitch BGA BA50 Top ViewLead Tqfp A100 Top View Ball Fine-Pitch BGA BB100 for CY37128V Top View Ball Fine-Pitch BGA BB100 for CY37064V Top ViewCLK3/I4 GND TDO I/O Lead Tqfp A160 for CY37192V Top ViewI/O I/O I/O I/O I/O I/O I/O I/O Lead Pqfp N208 / Cqfp U208 Top ViewBall Pbga BG292 Top View Ball Fine-Pitch BGA BB256 Top View Lead Pbga BG388 Top View Ball Fine-Pitch BGA BB400 Top View 0V Ordering Information Ordering InformationLead Plastic Leaded Chip Carrier CY37064P84-154JC CY37128P84-167JC Lead Plastic Quad Flat Pack CY37256P256-154BGC 3V Ordering Information BB100 Lead Plastic Quad Flat Pack CY37256VP256-100BGC Lead Lead Pb-Free Thin Plastic Quad Flat Pack A44 Package DiagramsLead Lead Pb-Free Plastic Leaded Chip Carrier J67 Lead Ceramic Leaded Chip Carrier Y67 Lead Lead Pb-Free Plastic Leaded Chip Carrier J83 Ball 7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch Thin BGA BA48DLead Ceramic Leaded Chip Carrier Y84 Lead Lead Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85049-*B Detail a Lead Ceramic Quad Flatpack Cavity Up U162Lead Plastic Quad Flatpack N208 Lead Ceramic Quad Flatpack Cavity Up U208 Bottom View Ball Fbga 17 x 17 mm BB256Ball Plastic Ball Grid Array Pbga 27 x 27 x 2.33 mm BG292 Ball Plastic Ball Grid Array Pbga 35 x 35 x 2.33 mm BG388 Ball Fbga 21 x 21 x 1.4 mm BB400 Commercial Addendum 3V Operating Range3V ± Document History Issue Orig. Description of Change Date
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