Cypress 37000 CPLD manual Selection Guide

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Ultra37000 CPLD Family

Selection Guide

5.0V Selection Guide

General Information

Device	Macrocells	Dedicated Inputs	I/O Pins	Speed (tPD)	Speed (fMAX)
CY37032	32	5	32	6	200

CY37064	64	5	32/64	6	200

CY37128	128	5	64/128	6.5	167

CY37192	192	5	120	7.5	154

CY37256	256	5	128/160/192	7.5	154

CY37384	384	5	160/192	10	118

CY37512	512	5	160/192/264	10	118

Speed Bins

Device		200				167				154			143			125					100				83		66
CY37032			X							X							X

CY37064			X							X							X

CY37128							X										X					X

CY37192										X							X								X

CY37256										X							X								X

CY37384																	X								X

CY37512																	X					X			X

Device-Package Offering and I/O Count

Device		44-			44-			44-		84-	84-			100-			160-		160-			208-			208-	292-			388-
Device		Lead			Lead			Lead		Lead	Lead			Lead			Lead		Lead			Lead			Lead	Lead			Lead
		TQFP			PLCC			CLCC		PLCC	CLCC			TQFP			TQFP		CQFP			PQFP			CQFP	PBGA			PBGA
CY37032		37			37

CY37064		37			37			37		69				69

CY37128										69	69			69			133

CY37192																	125

CY37256																	133		133			165				197

CY37384																						165				197

CY37512																						165			165	197			269

3.3V Selection Guide
General Information

Device				Macrocells						Dedicated Inputs							I/O Pins					Speed (tPD)				Speed (fMAX)
CY37032V				32							5					32					8.5					143

CY37064V				64							5					32/64					8.5					143

CY37128V				128							5					64/80/128					10					125

CY37192V				192							5					120					12					100

CY37256V				256							5					128/160/192					12					100

CY37384V				384							5					160/192					15					83

CY37512V				512							5					160/192/264					15					83

Document #: 38-03007 Rev. *E

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Contents Ultra37000V 3.3V Devices FeaturesUltra37000 5.0V Devices Cypress Semiconductor CorporationSelection Guide Logic Block Architecture Overview of Ultra37000 FamilyProgrammable Interconnect Matrix Product Term Allocator Ultra37000 MacrocellO and Buried Macrocells Input Macrocell Timing ModelDevelopment Software Support Jtag and PCI StandardsThird-Party Programmers CY37064/CY37064VInput Logic Block DiagramsCY37032/CY37032V CY37128/CY37128V CY37192/CY37192VLogic Block Diagrams CY37256/CY37256VCY37384/CY37384V TMSCY37512/CY37512V Range 0V Device Characteristics Maximum RatingsOperating Range2 Output ConditionInductance5 Endurance Characteristics53V Device Characteristics Maximum Ratings Capacitance5AC Characteristics Switching Characteristics Over the Operating Range Parameter Description Unit Product Term Clocking Parameters Pipelined Mode ParametersReset/Preset Parameters User Option ParametersProduct Term Reset/PresetSynchronous Operating Frequency ParametersJtag Timing Switching WaveformsUser Option Combinatorial OutputLatched Output Latched Input Registered InputClock to Clock Output Enable/Disable Asynchronous ResetAsynchronous Preset Latched Input and OutputCY37064 Power ConsumptionTypical 5.0V Power Consumption CY37032 Typical 5.0V Power Consumption CY37128 CY37192Typical 5.0V Power Consumption CY37256 CY37384Typical 5.0V Power Consumption CY37512 Typical 3.3V Power Consumption CY37032VTypical 3.3V Power Consumption CY37064V CY37128VTypical 3.3V Power Consumption CY37192V CY37256VTypical 3.3V Power Consumption CY37384V CY37512VPin Plcc J67 / Clcc Y67 Top View Pin Configurations20Pin Tqfp A44 Top View Ball Fine-Pitch BGA BA50 Top View Lead Plcc J83 / Clcc Y84 Top ViewLead Tqfp A100 Top View Ball Fine-Pitch BGA BB100 for CY37064V Top View Ball Fine-Pitch BGA BB100 for CY37128V Top ViewCLK3/I4 GND Lead Tqfp A160 for CY37192V Top View TDO I/OLead Pqfp N208 / Cqfp U208 Top View I/O I/O I/O I/O I/O I/O I/O I/OBall Pbga BG292 Top View Ball Fine-Pitch BGA BB256 Top View Lead Pbga BG388 Top View Ball Fine-Pitch BGA BB400 Top View Ordering Information 0V Ordering InformationLead Plastic Leaded Chip Carrier CY37064P84-154JC CY37128P84-167JC Lead Plastic Quad Flat Pack CY37256P256-154BGC 3V Ordering Information BB100 Lead Plastic Quad Flat Pack CY37256VP256-100BGC Lead Lead Pb-Free Plastic Leaded Chip Carrier J67 Package DiagramsLead Lead Pb-Free Thin Plastic Quad Flat Pack A44 Lead Ceramic Leaded Chip Carrier Y67 Ball 7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch Thin BGA BA48D Lead Lead Pb-Free Plastic Leaded Chip Carrier J83Lead Ceramic Leaded Chip Carrier Y84 Lead Lead Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85049-*B Lead Ceramic Quad Flatpack Cavity Up U162 Detail aLead Plastic Quad Flatpack N208 Lead Ceramic Quad Flatpack Cavity Up U208 Ball Fbga 17 x 17 mm BB256 Bottom ViewBall Plastic Ball Grid Array Pbga 27 x 27 x 2.33 mm BG292 Ball Plastic Ball Grid Array Pbga 35 x 35 x 2.33 mm BG388 Ball Fbga 21 x 21 x 1.4 mm BB400 3V ± Addendum 3V Operating RangeCommercial Issue Orig. Description of Change Date Document History