Cypress 37000 CPLD manual Inductance5, Capacitance5, Endurance Characteristics5

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Ultra37000 CPLD Family

Inductance[5]

Parameter

Description

Test Conditions

44-Lead

44-Lead

44-Lead

84-Lead

84-Lead

100-Lead

 

160-Lead

208-Lead

Unit

TQFP

 

PLCC

CLCC

 

PLCC

CLCC

 

TQFP

 

TQFP

PQFP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

Maximum Pin

VIN = 5.0V

2

 

 

 

5

 

2

 

8

 

5

 

8

 

9

 

11

nH

 

Inductance

 

at f = 1 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Capacitance[5]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

Description

 

 

 

 

Test Conditions

 

 

 

 

Max.

 

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CI/O

 

 

Input/Output Capacitance

 

VIN = 5.0V at f = 1

MHz at TA = 25°C

 

 

 

 

10

 

 

 

pF

 

CCLK

 

 

Clock Signal Capacitance

 

VIN = 5.0V at f = 1

MHz at TA = 25°C

 

 

 

 

12

 

 

 

pF

 

C

 

 

Dual-Function Pins[9]

 

 

 

V

IN

= 5.0V at f = 1

MHz at T

= 25°C

 

 

 

 

16

 

 

 

pF

 

DP

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

Endurance Characteristics[5]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

Description

 

 

 

 

 

 

Test Conditions

 

 

 

 

Min.

 

Typ.

 

Unit

 

 

 

 

 

 

 

 

 

 

 

N

 

Minimum Reprogramming Cycles

 

 

Normal Programming Conditions[2]

 

1,000

10,000

 

Cycles

3.3V Device Characteristics

Maximum Ratings

(Above which the useful life may be impaired. For user guide- lines, not tested.)

Storage Temperature

–65°C to +150°C

Ambient Temperature with

–55°C to +125°C

Power Applied

Supply Voltage to Ground Potential

–0.5V to +4.6V

DC Voltage Applied to Outputs

 

in High-Z State

–0.5V to +7.0V

DC Input Voltage

–0.5V to +7.0V

DC Program Voltage

3.0 to 3.6V

Current into Outputs

8 mA

Static Discharge Voltage

> 2001V

(per MIL-STD-883, Method 3015)

 

Latch-up Current

> 200 mA

Operating Range[2]

Range

Ambient Temperature[2]

Junction Temperature

VCC[10]

Commercial

0°C to +70°C

0°C to +90°C

3.3V ± 0.3V

 

 

 

 

Industrial

–40°C to +85°C

–40°C to +105°C

3.3V ± 0.3V

 

 

 

 

Military[3]

–55°C to +125°C

–55°C to +130°C

3.3V ± 0.3V

3.3V Device Electrical Characteristics Over the Operating Range

Parameter

Description

 

 

 

Test Conditions

Min.

Max.

Unit

V

OH

Output HIGH Voltage

V

CC

= Min.

 

I = –4 mA (Com’l)[4]

2.4

 

V

 

 

 

 

 

OH

 

 

 

 

 

 

 

 

 

 

I = –3 mA (Mil)[4]

 

 

 

 

 

 

 

 

 

 

OH

 

 

 

VOL

Output LOW Voltage

VCC = Min.

 

IOL = 8 mA (Com’l)[4]

 

0.5

V

 

 

 

 

 

 

 

IOL = 6 mA (Mil)[4]

 

 

 

VIH

Input HIGH Voltage

Guaranteed

Input Logical HIGH Voltage for

2.0

5.5

V

 

 

 

all Inputs[7]

 

 

 

 

 

VIL

Input LOW Voltage

Guaranteed Input Logical LOW Voltage for

–0.5

0.8

V

 

 

 

all Inputs[7]

 

 

 

 

 

IIX

Input Load Current

VI = GND OR VCC, Bus-Hold Disabled

–10

10

A

IOZ

Output Leakage Current

VO = GND or VCC, Output Disabled,

–50

50

A

 

 

 

Bus-Hold Disabled

 

 

 

IOS

Output Short Circuit Current[5, 8]

VCC = Max., VOUT = 0.5V

–30

–160

mA

IBHL

Input Bus-Hold LOW Sustaining Current

VCC = Min., VIL = 0.8V

+75

 

A

IBHH

Input Bus-Hold HIGH Sustaining Current

VCC = Min., VIH = 2.0V

–75

 

A

IBHLO

Input Bus-Hold LOW Overdrive Current

VCC = Max.

 

 

 

+500

A

IBHHO

Input Bus-Hold HIGH Overdrive Current

VCC = Max.

 

 

 

–500

A

Notes:

9. Dual pins are I/O with JTAG pins.

10. For CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC; Operating Range: VCC is 3.3V± 0.16V.

Document #: 38-03007 Rev. *E

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Contents Cypress Semiconductor Corporation FeaturesUltra37000 5.0V Devices Ultra37000V 3.3V DevicesSelection Guide Architecture Overview of Ultra37000 Family Programmable Interconnect MatrixLogic Block Ultra37000 Macrocell Product Term AllocatorO and Buried Macrocells Timing Model Input MacrocellJtag and PCI Standards Development Software SupportThird-Party Programmers Logic Block Diagrams CY37032/CY37032VCY37064/CY37064VInput CY37192/CY37192V CY37128/CY37128VCY37256/CY37256V Logic Block DiagramsTMS CY37384/CY37384VCY37512/CY37512V Output Condition 0V Device Characteristics Maximum RatingsOperating Range2 RangeCapacitance5 Endurance Characteristics53V Device Characteristics Maximum Ratings Inductance5AC Characteristics Switching Characteristics Over the Operating Range User Option Parameters Pipelined Mode ParametersReset/Preset Parameters Parameter Description Unit Product Term Clocking ParametersOperating Frequency Parameters Reset/PresetSynchronous Product TermCombinatorial Output Switching WaveformsUser Option Jtag TimingLatched Output Registered Input Clock to ClockLatched Input Latched Input and Output Asynchronous ResetAsynchronous Preset Output Enable/DisablePower Consumption Typical 5.0V Power Consumption CY37032CY37064 CY37192 Typical 5.0V Power Consumption CY37128CY37384 Typical 5.0V Power Consumption CY37256Typical 3.3V Power Consumption CY37032V Typical 5.0V Power Consumption CY37512CY37128V Typical 3.3V Power Consumption CY37064VCY37256V Typical 3.3V Power Consumption CY37192VCY37512V Typical 3.3V Power Consumption CY37384VPin Configurations20 Pin Tqfp A44 Top ViewPin Plcc J67 / Clcc Y67 Top View Lead Plcc J83 / Clcc Y84 Top View Ball Fine-Pitch BGA BA50 Top ViewLead Tqfp A100 Top View Ball Fine-Pitch BGA BB100 for CY37128V Top View Ball Fine-Pitch BGA BB100 for CY37064V Top ViewCLK3/I4 GND TDO I/O Lead Tqfp A160 for CY37192V Top ViewI/O I/O I/O I/O I/O I/O I/O I/O Lead Pqfp N208 / Cqfp U208 Top ViewBall Pbga BG292 Top View Ball Fine-Pitch BGA BB256 Top View Lead Pbga BG388 Top View Ball Fine-Pitch BGA BB400 Top View 0V Ordering Information Ordering InformationLead Plastic Leaded Chip Carrier CY37064P84-154JC CY37128P84-167JC Lead Plastic Quad Flat Pack CY37256P256-154BGC 3V Ordering Information BB100 Lead Plastic Quad Flat Pack CY37256VP256-100BGC Package Diagrams Lead Lead Pb-Free Thin Plastic Quad Flat Pack A44Lead Lead Pb-Free Plastic Leaded Chip Carrier J67 Lead Ceramic Leaded Chip Carrier Y67 Lead Lead Pb-Free Plastic Leaded Chip Carrier J83 Ball 7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch Thin BGA BA48DLead Ceramic Leaded Chip Carrier Y84 Lead Lead Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85049-*B Detail a Lead Ceramic Quad Flatpack Cavity Up U162Lead Plastic Quad Flatpack N208 Lead Ceramic Quad Flatpack Cavity Up U208 Bottom View Ball Fbga 17 x 17 mm BB256Ball Plastic Ball Grid Array Pbga 27 x 27 x 2.33 mm BG292 Ball Plastic Ball Grid Array Pbga 35 x 35 x 2.33 mm BG388 Ball Fbga 21 x 21 x 1.4 mm BB400 Addendum 3V Operating Range Commercial3V ± Document History Issue Orig. Description of Change Date