Cypress 37000 CPLD manual Lead Ceramic Quad Flatpack Cavity Up U162, Detail a

Page 56

Ultra37000 CPLD Family

Package Diagrams (continued)

160-Lead Ceramic Quad Flatpack (Cavity Up) U162

25.35±0.10

(.998±.004)

TYP.

PIN 1

28.00 ±0.10

(1.102 ±.004) SQ.

31.20 ±0.25

(1.228 ±.010) SQ.

SEATING PLANE

2.03(.080)

2.79(.110)

0.050(.002)

0.500(.020)

DIMENSION IN MM (INCH)

REFERENCE JEDEC: N/A

PKG. WEIGHT: 6-7gms

0.650(.0256)

TYP.

0.300(.012)

TYP.

R 0.13(.005)

MIN.

0° -7°

0.20 MIN.

(.008 MIN.)

0° MIN.

DETAIL A

SEE DETAIL A

0.15±0.02

(.006 ±.001)

0.51±0.20

(.020 ±.008)

51-80106-*A

Document #: 38-03007 Rev. *E

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Contents Features Ultra37000 5.0V DevicesUltra37000V 3.3V Devices Cypress Semiconductor CorporationSelection Guide Logic Block Architecture Overview of Ultra37000 FamilyProgrammable Interconnect Matrix Product Term Allocator Ultra37000 MacrocellO and Buried Macrocells Input Macrocell Timing ModelDevelopment Software Support Jtag and PCI StandardsThird-Party Programmers CY37064/CY37064VInput Logic Block DiagramsCY37032/CY37032V CY37128/CY37128V CY37192/CY37192VLogic Block Diagrams CY37256/CY37256VCY37384/CY37384V TMSCY37512/CY37512V 0V Device Characteristics Maximum Ratings Operating Range2Range Output ConditionEndurance Characteristics5 3V Device Characteristics Maximum RatingsInductance5 Capacitance5AC Characteristics Switching Characteristics Over the Operating Range Pipelined Mode Parameters Reset/Preset ParametersParameter Description Unit Product Term Clocking Parameters User Option ParametersReset/Preset SynchronousProduct Term Operating Frequency ParametersSwitching Waveforms User OptionJtag Timing Combinatorial OutputLatched Output Latched Input Registered InputClock to Clock Asynchronous Reset Asynchronous PresetOutput Enable/Disable Latched Input and OutputCY37064 Power ConsumptionTypical 5.0V Power Consumption CY37032 Typical 5.0V Power Consumption CY37128 CY37192Typical 5.0V Power Consumption CY37256 CY37384Typical 5.0V Power Consumption CY37512 Typical 3.3V Power Consumption CY37032VTypical 3.3V Power Consumption CY37064V CY37128VTypical 3.3V Power Consumption CY37192V CY37256VTypical 3.3V Power Consumption CY37384V CY37512VPin Plcc J67 / Clcc Y67 Top View Pin Configurations20Pin Tqfp A44 Top View Ball Fine-Pitch BGA BA50 Top View Lead Plcc J83 / Clcc Y84 Top ViewLead Tqfp A100 Top View Ball Fine-Pitch BGA BB100 for CY37064V Top View Ball Fine-Pitch BGA BB100 for CY37128V Top ViewCLK3/I4 GND Lead Tqfp A160 for CY37192V Top View TDO I/OLead Pqfp N208 / Cqfp U208 Top View I/O I/O I/O I/O I/O I/O I/O I/OBall Pbga BG292 Top View Ball Fine-Pitch BGA BB256 Top View Lead Pbga BG388 Top View Ball Fine-Pitch BGA BB400 Top View Ordering Information 0V Ordering InformationLead Plastic Leaded Chip Carrier CY37064P84-154JC CY37128P84-167JC Lead Plastic Quad Flat Pack CY37256P256-154BGC 3V Ordering Information BB100 Lead Plastic Quad Flat Pack CY37256VP256-100BGC Lead Lead Pb-Free Plastic Leaded Chip Carrier J67 Package DiagramsLead Lead Pb-Free Thin Plastic Quad Flat Pack A44 Lead Ceramic Leaded Chip Carrier Y67 Ball 7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch Thin BGA BA48D Lead Lead Pb-Free Plastic Leaded Chip Carrier J83Lead Ceramic Leaded Chip Carrier Y84 Lead Lead Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85049-*B Lead Ceramic Quad Flatpack Cavity Up U162 Detail aLead Plastic Quad Flatpack N208 Lead Ceramic Quad Flatpack Cavity Up U208 Ball Fbga 17 x 17 mm BB256 Bottom ViewBall Plastic Ball Grid Array Pbga 27 x 27 x 2.33 mm BG292 Ball Plastic Ball Grid Array Pbga 35 x 35 x 2.33 mm BG388 Ball Fbga 21 x 21 x 1.4 mm BB400 3V ± Addendum 3V Operating RangeCommercial Issue Orig. Description of Change Date Document History