Cypress 37000 CPLD manual Product Term Allocator, Ultra37000 Macrocell

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Ultra37000 CPLD Family

 

 

 

 

 

3

2

2

 

 

 

 

016

MACRO-

I/O

 

 

 

 

 

PRODUCT

CELL

CELL

 

 

 

 

 

0

0

 

 

 

 

 

TERMS

 

 

 

 

 

 

 

 

 

 

 

7

016

MACRO-

 

 

 

 

 

 

 

 

 

 

 

 

 

CELL

to cells

 

 

 

 

 

PRODUCT

1

2, 4, 6 8, 10, 12

 

 

 

 

TERMS

 

 

 

FROM

 

 

 

 

 

 

 

PIM

36

72 x 87

80

PRODUCT

 

 

 

 

 

PRODUCT TERM

 

TERM

 

 

 

 

 

ARRAY

 

ALLOCATOR

 

 

 

 

 

 

 

016

MACRO-

I/O

 

 

 

 

 

 

CELL

CELL

 

 

 

 

 

PRODUCT

14

14

 

 

 

 

 

TERMS

 

 

 

 

 

 

 

016

MACRO-

 

 

TO

 

 

 

 

CELL

 

 

 

 

 

PRODUCT

15

 

 

PIM

 

 

16

TERMS

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

Figure 1. Logic Block with 50% Buried Macrocells

Low-Power Option

Each logic block can operate in high-speed mode for critical path performance, or in low-power mode for power conser- vation. The logic block mode is set by the user on a logic block by logic block basis.

Product Term Allocator

Through the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block as needed. A total of 80 product terms are available from the local product term array. The product term allocator provides two important capabilities without affecting perfor- mance: product term steering and product term sharing.

Product Term Steering

Product term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will “steer” ten product terms to one macrocell and three to the other. On Ultra37000 devices, product terms are steered on an individual basis. Any number between 0 and 16 product terms can be steered to any macrocell. Note that 0 product terms is useful in cases where a particular macrocell is unused or used as an input register.

Product Term Sharing

Product term sharing is the process of using the same product term among multiple macrocells. For example, if more than one output has one or more product terms in its equation that are common to other outputs, those product terms are only programmed once. The Ultra37000 product term allocator allows sharing across groups of four output macrocells in a

variable fashion. The software automatically takes advantage of this capability—the user does not have to intervene.

Note that neither product term sharing nor product term steering have any effect on the speed of the product. All worst-case steering and sharing configurations have been incorporated in the timing specifications for the Ultra37000 devices.

Ultra37000 Macrocell

Within each logic block there are 16 macrocells. Macrocells can either be I/O Macrocells, which include an I/O Cell which is associated with an I/O pin, or buried Macrocells, which do not connect to an I/O. The combination of I/O Macrocells and buried Macrocells varies from device to device.

Buried Macrocell

Figure 2 displays the architecture of buried macrocells. The buried macrocell features a register that can be configured as combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch.

The register can be asynchronously set or asynchronously reset at the logic block level with the separate set and reset product terms. Each of these product terms features program- mable polarity. This allows the registers to be set or reset based on an AND expression or an OR expression.

Clocking of the register is very flexible. Four global synchronous clocks and a product term clock are available to clock the register. Furthermore, each clock features program- mable polarity so that registers can be triggered on falling as well as rising edges (see the Clocking section). Clock polarity is chosen at the logic block level.

Document #: 38-03007 Rev. *E

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Contents Features Ultra37000 5.0V DevicesUltra37000V 3.3V Devices Cypress Semiconductor CorporationSelection Guide Programmable Interconnect Matrix Architecture Overview of Ultra37000 FamilyLogic Block Product Term Allocator Ultra37000 MacrocellO and Buried Macrocells Input Macrocell Timing ModelDevelopment Software Support Jtag and PCI StandardsThird-Party Programmers CY37032/CY37032V Logic Block DiagramsCY37064/CY37064VInput CY37128/CY37128V CY37192/CY37192VLogic Block Diagrams CY37256/CY37256VCY37384/CY37384V TMSCY37512/CY37512V 0V Device Characteristics Maximum Ratings Operating Range2Range Output ConditionEndurance Characteristics5 3V Device Characteristics Maximum RatingsInductance5 Capacitance5AC Characteristics Switching Characteristics Over the Operating Range Pipelined Mode Parameters Reset/Preset ParametersParameter Description Unit Product Term Clocking Parameters User Option ParametersReset/Preset SynchronousProduct Term Operating Frequency ParametersSwitching Waveforms User OptionJtag Timing Combinatorial OutputLatched Output Clock to Clock Registered InputLatched Input Asynchronous Reset Asynchronous PresetOutput Enable/Disable Latched Input and OutputTypical 5.0V Power Consumption CY37032 Power ConsumptionCY37064 Typical 5.0V Power Consumption CY37128 CY37192Typical 5.0V Power Consumption CY37256 CY37384Typical 5.0V Power Consumption CY37512 Typical 3.3V Power Consumption CY37032VTypical 3.3V Power Consumption CY37064V CY37128VTypical 3.3V Power Consumption CY37192V CY37256VTypical 3.3V Power Consumption CY37384V CY37512VPin Tqfp A44 Top View Pin Configurations20Pin Plcc J67 / Clcc Y67 Top View Ball Fine-Pitch BGA BA50 Top View Lead Plcc J83 / Clcc Y84 Top ViewLead Tqfp A100 Top View Ball Fine-Pitch BGA BB100 for CY37064V Top View Ball Fine-Pitch BGA BB100 for CY37128V Top ViewCLK3/I4 GND Lead Tqfp A160 for CY37192V Top View TDO I/OLead Pqfp N208 / Cqfp U208 Top View I/O I/O I/O I/O I/O I/O I/O I/OBall Pbga BG292 Top View Ball Fine-Pitch BGA BB256 Top View Lead Pbga BG388 Top View Ball Fine-Pitch BGA BB400 Top View Ordering Information 0V Ordering InformationLead Plastic Leaded Chip Carrier CY37064P84-154JC CY37128P84-167JC Lead Plastic Quad Flat Pack CY37256P256-154BGC 3V Ordering Information BB100 Lead Plastic Quad Flat Pack CY37256VP256-100BGC Lead Lead Pb-Free Thin Plastic Quad Flat Pack A44 Package DiagramsLead Lead Pb-Free Plastic Leaded Chip Carrier J67 Lead Ceramic Leaded Chip Carrier Y67 Ball 7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch Thin BGA BA48D Lead Lead Pb-Free Plastic Leaded Chip Carrier J83Lead Ceramic Leaded Chip Carrier Y84 Lead Lead Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85049-*B Lead Ceramic Quad Flatpack Cavity Up U162 Detail aLead Plastic Quad Flatpack N208 Lead Ceramic Quad Flatpack Cavity Up U208 Ball Fbga 17 x 17 mm BB256 Bottom ViewBall Plastic Ball Grid Array Pbga 27 x 27 x 2.33 mm BG292 Ball Plastic Ball Grid Array Pbga 35 x 35 x 2.33 mm BG388 Ball Fbga 21 x 21 x 1.4 mm BB400 Commercial Addendum 3V Operating Range3V ± Issue Orig. Description of Change Date Document History