Cypress CY7C1318CV18-267BZXC, 001-07160 Identification Register Definitions, Scan Register Sizes

Page 15

 

 

 

 

 

 

CY7C1318CV18

 

 

 

 

 

 

CY7C1320CV18

 

 

 

 

 

 

Identification Register Definitions

 

 

 

 

 

 

 

 

 

 

Instruction Field

 

 

 

Value

Description

 

 

CY7C1318CV18

 

CY7C1320CV18

 

 

 

 

 

Revision Number (31:29)

000

 

000

Version number.

 

 

 

 

 

Cypress Device ID (28:12)

11010100010010101

 

11010100010100101

Defines the type of SRAM.

 

 

 

 

 

Cypress JEDEC ID (11:1)

00000110100

 

00000110100

Allows unique identification of

 

 

 

 

 

 

SRAM vendor.

ID Register Presence (0)

1

 

1

Indicates the presence of an

 

 

 

 

 

 

ID register.

Scan Register Sizes

Register Name

Bit Size

Instruction

3

 

 

Bypass

1

 

 

ID

32

 

 

Boundary Scan

107

 

 

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the input and output ring contents.

 

 

 

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

 

 

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and

 

 

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

 

 

 

SAMPLE/PRELOAD

100

Captures the input and output ring contents. Places the boundary scan register between TDI

 

 

and TDO. Does not affect the SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

 

 

 

RESERVED

110

Do Not Use: This instruction is reserved for future use.

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

operation.

Document Number: 001-07160 Rev. *F

Page 15 of 26

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1320CV18 Logic Block Diagram CY7C1318CV18CY7C1320CV18 512K x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1318CV18 1M xReferenced with Respect to Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. WhenTCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview SRAM#1 ZQ Application ExampleProgrammable Impedance Echo ClocksComments Write Cycle DescriptionsOperation First Address External Second Address InternalDevice. D80 and D3518 remains unaltered Write cycle description table for CY7C1320CV18 follows.2Device Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence in DDR II Sram Power Up SequenceDLL Constraints Maximum Ratings Neutron Soft Error ImmunityElectrical Characteristics DC Electrical CharacteristicsParameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal ResistanceParameter Min Max DLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence26, 27 Switching WaveformsOrdering Information CY7C1320CV18-267BZXCCY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History Worldwide Sales and Design Support Products Sales, Solutions, and Legal Information