Cypress CY7C1320CV18-200BZC, CY7C1320CV18-250BZC manual Package Diagram, Ball Fbga 13 x 15 x 1.4 mm

Page 24

CY7C1318CV18

CY7C1320CV18

Package Diagram

Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180

15.00±0.10

A

TOP VIEW

PIN 1 CORNER

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

1.00

15.00±0.10

14.00

 

7.00

A

BOTTOM VIEW

PIN 1 CORNER

Ø0.08 M C

Ø0.25 M C A B

-0.06

Ø0.50 (165X)

+0.14

11

10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

1.00

5.00

0.25 C

 

B

0.53±0.05

 

0.36

C

 

13.00±0.10

 

1.40MAX.

 

 

 

 

0.15C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SEATING PLANE

0.35±0.06

B

0.15(4X)

10.00

13.00±0.10

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / ISSUE E PACKAGE CODE : BB0AC

51-85180-*B

Document Number: 001-07160 Rev. *F

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1318CV18 Logic Block Diagram CY7C1320CV18Pin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutCY7C1318CV18 1M x CY7C1320CV18 512K xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Referenced with Respect toPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Application Example Programmable ImpedanceEcho Clocks SRAM#1 ZQWrite Cycle Descriptions OperationFirst Address External Second Address Internal CommentsWrite cycle description table for CY7C1320CV18 follows.2 DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows.9TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in DDR II Sram Power Up SequenceDLL Constraints Neutron Soft Error Immunity Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsAC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms Read/Write/Deselect Sequence26, 27Ordering Information CY7C1320CV18-267BZXCCY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products
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