Cypress CY7C1318CV18-167BZC manual Maximum Ratings, Neutron Soft Error Immunity, Operating Range

Page 18

CY7C1318CV18

CY7C1320CV18

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND

–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND

–0.5V to +VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.3V

DC Input Voltage[11]

–0.5V to VDD + 0.3V

Current into Outputs (LOW)

20 mA

Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V

Latch up Current

>200 mA

Neutron Soft Error Immunity

Parameter

Description

Test

Typ

Max*

Unit

Conditions

LSBU

Logical

25°C

320

368

FIT/

 

Single-Bit

 

 

 

Mb

 

Upsets

 

 

 

 

LMBU

Logical

25°C

0

0.01

FIT/

 

Multi-Bit

 

 

 

Mb

 

Upsets

 

 

 

 

SEL

Single Event

85°C

0

0.1

FIT/

 

Latch up

 

 

 

Dev

*No LMBU or SEL events occurred during testing; this column represents a statistical χ2, 95% confidence limit calculation. For more details refer to Appli- cation Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates”

Operating Range

Range

Ambient

V

 

[15]

V

[15]

Temperature (T )

DD

 

A

 

 

 

DDQ

Commercial

0°C to +70°C

1.8 ± 0.1V

1.4V to

 

 

 

 

 

 

VDD

Industrial

–40°C to +85°C

 

 

 

 

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range[12]

Parameter

Description

Test Conditions

 

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

 

1.7

1.8

1.9

V

VDDQ

I/O Supply Voltage

 

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 16

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 17

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = 0.1 mA, Nominal Impedance

 

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

 

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

 

VREF + 0.1

 

VDDQ + 0.3

V

VIL

Input LOW Voltage

 

 

 

–0.3

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

 

5

 

5

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

 

5

 

5

μA

VREF

Input Reference Voltage[18]

Typical Value = 0.75V

 

 

0.68

0.75

0.95

V

IDD[19]

VDD Operating Supply

VDD = Max,

267 MHz

(x18)

 

 

805

mA

 

 

IOUT = 0 mA,

 

 

 

 

 

 

 

 

 

(x36)

 

 

855

 

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

250 MHz

(x18)

 

 

730

 

 

 

 

 

(x36)

 

 

775

 

 

 

 

200 MHz

(x18)

 

 

600

 

 

 

 

 

(x36)

 

 

635

 

 

 

 

167 MHz

(x18)

 

 

510

 

 

 

 

 

(x36)

 

 

540

 

Notes

15.Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

16.Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

17.Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

18.VREF(min) = 0.68V or 0.46VDDQ, whichever is larger, VREF(max) = 0.95V or 0.54VDDQ, whichever is smaller.

19.The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-07160 Rev. *F

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1318CV18 Logic Block Diagram CY7C1320CV18CY7C1318CV18 1M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1320CV18 512K xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Referenced with Respect toTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Echo Clocks Application ExampleProgrammable Impedance SRAM#1 ZQFirst Address External Second Address Internal Write Cycle DescriptionsOperation CommentsInto the device. D359 remains unaltered Write cycle description table for CY7C1320CV18 follows.2Device Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows.9TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in DDR II Sram Power Up SequenceDLL Constraints DC Electrical Characteristics Neutron Soft Error ImmunityElectrical Characteristics Maximum RatingsThermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms Read/Write/Deselect Sequence26, 27Ordering Information CY7C1320CV18-267BZXCCY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products