Cypress CY7C1320CV18-267BZXC, CY7C1320CV18-200BZC manual Sales, Solutions, and Legal Information

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CY7C1318CV18

CY7C1320CV18

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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-07160 Rev. *F

Revised August 24, 2009

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QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1318CV18 Logic Block Diagram CY7C1320CV18CY7C1318CV18 1M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1320CV18 512K xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Referenced with Respect toTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Echo Clocks Application ExampleProgrammable Impedance SRAM#1 ZQFirst Address External Second Address Internal Write Cycle DescriptionsOperation CommentsInto the device. D359 remains unaltered Write cycle description table for CY7C1320CV18 follows.2Device Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows.9TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in DDR II SramPower Up Sequence DC Electrical Characteristics Neutron Soft Error ImmunityElectrical Characteristics Maximum RatingsThermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms Read/Write/Deselect Sequence26, 27CY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Ordering InformationCY7C1320CV18-267BZXC Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products