Cypress 001-07160, CY7C1320CV18-200BZC manual Ordering Information, CY7C1320CV18-267BZXC

Page 23

CY7C1318CV18

CY7C1320CV18

Ordering Information

The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices

Table 1. Ordering Information

Speed

Ordering Code

Package

Package Type

Operating

(MHz)

Diagram

Range

267

CY7C1318CV18-267BZXC

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

Commercial

 

 

 

 

 

 

CY7C1320CV18-267BZXC

 

 

 

 

 

 

 

 

250

CY7C1318CV18-250BZC

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Commercial

 

 

 

 

 

 

CY7C1320CV18-250BZC

 

 

 

 

 

 

 

 

 

CY7C1318CV18-250BZXC

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

 

 

 

 

 

 

 

CY7C1320CV18-250BZXC

 

 

 

 

 

 

 

 

200

CY7C1320CV18-200BZC

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Commercial

 

 

 

 

 

 

CY7C1318CV18-200BZXC

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

 

 

 

 

 

 

 

CY7C1318CV18-200BZI

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Industrial

 

 

 

 

 

167

CY7C1318CV18-167BZC

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Commercial

 

 

 

 

 

 

CY7C1320CV18-167BZC

 

 

 

 

 

 

 

 

Document Number: 001-07160 Rev. *F

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1320CV18 Logic Block Diagram CY7C1318CV18CY7C1320CV18 512K x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1318CV18 1M xReferenced with Respect to Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. WhenTCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview SRAM#1 ZQ Application ExampleProgrammable Impedance Echo ClocksComments Write Cycle DescriptionsOperation First Address External Second Address InternalDevice. D80 and D3518 remains unaltered Write cycle description table for CY7C1320CV18 follows.2Device Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR II SramPower Up Sequence Maximum Ratings Neutron Soft Error ImmunityElectrical Characteristics DC Electrical CharacteristicsParameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal ResistanceParameter Min Max DLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence26, 27 Switching WaveformsCY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Ordering InformationCY7C1320CV18-267BZXC Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History Worldwide Sales and Design Support Products Sales, Solutions, and Legal Information
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