Cypress CY7C1320CV18-267BZXC Logic Block Diagram CY7C1318CV18, Logic Block Diagram CY7C1320CV18

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CY7C1318CV18

CY7C1320CV18

Logic Block Diagram (CY7C1318CV18)

Burst

Logic

A(19:0)

A(19:1)

Address

CLK

K Gen.

DOFF

VREF
		Control


R/W
R/W		Logic
		Logic
BWS
BWS	[1:0]

	Write	Write
DecodeAdd.Write	Reg	Reg	DecodeAdd.Read
DecodeAdd.Write	512Kx18Array	512Kx18Array	DecodeAdd.Read	Logic	18
					18
				Output	R/W
	Read Data Reg.			Control	C
	Read Data Reg.				C
					C

36
36
	18	Reg.		Reg.	18		CQ
	18	Reg.		Reg.	18		CQ
18						18	CQ


		Reg.	18				DQ[17:0]

Logic Block Diagram (CY7C1320CV18)

Burst

Logic

A(18:0)

A(18:1)

Address

CLK

K Gen.

DOFF

VREF
		Control


R/W
R/W		Logic
		Logic
BWS
BWS	[3:0]

	Write	Write
DecodeAdd.Write	Reg	Reg	DecodeAdd.Read
DecodeAdd.Write	256Kx36Array	256Kx36Array	DecodeAdd.Read	Logic	36
					36
				Output	R/W
	Read Data Reg.			Control	C
	Read Data Reg.				C
					C

72
72
	36	Reg.		Reg.	36		CQ
	36	Reg.		Reg.	36		CQ
36						36	CQ


		Reg.	36				DQ[35:0]

Document Number: 001-07160 Rev. *F

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1318CV18 Logic Block Diagram CY7C1320CV18CY7C1318CV18 1M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1320CV18 512K xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Referenced with Respect toTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Echo Clocks Application ExampleProgrammable Impedance SRAM#1 ZQFirst Address External Second Address Internal Write Cycle DescriptionsOperation CommentsInto the device. D359 remains unaltered Write cycle description table for CY7C1320CV18 follows.2Device Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows.9TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in DDR II SramPower Up Sequence DC Electrical Characteristics Neutron Soft Error ImmunityElectrical Characteristics Maximum RatingsThermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms Read/Write/Deselect Sequence26, 27CY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Ordering InformationCY7C1320CV18-267BZXC Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products