Cypress CY7C1318CV18-250BZXC, CY7C1320CV18-200BZC manual Parameter Min Max Output Times, DLL Timing

Page 21

CY7C1318CV18

CY7C1320CV18

Switching Characteristics (continued)

Over the Operating Range[20, 21]

Cypress

Consortium

 

 

 

 

 

Description

267 MHz

250 MHz

200 MHz

167 MHz

Unit

Parameter

Parameter

 

 

 

 

 

Min

Max

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCO

tCHQV

C/C

Clock Rise (or K/K in single clock mode) to

–

0.45

–

0.45

–

0.45

–

0.50

ns

 

 

 

 

Data Valid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDOH

tCHQX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Output Hold after Output C/C

Clock Rise

–0.45

–

–0.45

–

–0.45

–

–0.50

–

ns

 

 

 

 

(Active to Active)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCCQO

tCHCQV

 

 

Clock Rise to Echo Clock Valid

–

0.45

–

0.45

–

0.45

–

0.50

ns

C/C

tCQOH

tCHCQX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Echo Clock Hold after C/C

Clock Rise

–0.45

–

–0.45

–

–0.45

–

–0.50

–

ns

tCQD

tCQHQV

Echo Clock High to Data Valid

–

0.27

–

0.30

–

0.35

–

0.40

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.27

–

–0.30

–

–0.35

–

–0.40

–

ns

tCQH

tCQHCQL

 

 

 

 

 

 

 

 

 

HIGH[23]

1.43

–

1.55

–

1.95

–

2.45

–

ns

Output Clock (CQ/CQ)

tCQHCQH

 

tCQHCQH

 

CQ Clock Rise to

 

 

Clock Rise

1.43

–

1.55

–

1.95

–

2.45

–

ns

 

 

CQ

 

 

 

 

(rising edge to rising edge)[23]

 

 

 

 

 

 

 

 

 

tCHZ

tCHQZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock (C/C)

Rise to High-Z

–

0.45

–

0.45

–

0.45

–

0.50

ns

 

 

 

 

(Active to High-Z)[24, 25]

 

 

 

 

 

 

 

 

 

tCLZ

tCHQX1

 

 

 

 

 

Rise to Low-Z[24, 25]

 

 

 

 

 

 

 

 

 

Clock (C/C)

–0.45

–

–0.45

–

–0.45

–

–0.50

–

ns

DLL Timing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKC Var

tKC Var

Clock Phase Jitter

–

0.20

–

0.20

–

0.20

–

0.20

ns

tKC lock

tKC lock

DLL Lock Time (K, C)

1024

–

1024

–

1024

–

1024

–

Cycles

tKC Reset

tKC Reset

K Static to DLL Reset

30

–

30

–

30

–

30

–

ns

Notes

23.These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production.

24.tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±100 mV from steady-state voltage.

25.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

Document Number: 001-07160 Rev. *F

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1320CV18 Logic Block Diagram CY7C1318CV18Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1318CV18 1M x CY7C1320CV18 512K xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Referenced with Respect toPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Programmable Impedance Application ExampleEcho Clocks SRAM#1 ZQOperation Write Cycle DescriptionsFirst Address External Second Address Internal CommentsDevice Write cycle description table for CY7C1320CV18 follows.2Into the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence in DDR II Sram Power Up SequenceDLL Constraints Electrical Characteristics Neutron Soft Error ImmunityDC Electrical Characteristics Maximum RatingsCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max DLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence26, 27 Switching WaveformsOrdering Information CY7C1320CV18-267BZXCCY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History Worldwide Sales and Design Support Products Sales, Solutions, and Legal Information
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