Cypress CY7C1318CV18-267BZXC, 001-07160 manual Pin Configuration, Ball Fbga 13 x 15 x 1.4 mm Pinout

Page 3

CY7C1318CV18

CY7C1320CV18

Pin Configuration

The pin configuration for CY7C1318CV18 and CY7C1320CV18 follow.[1]

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1318CV18 (1M x 18)

 

 

1

 

 

2

3

4

 

5

 

6

 

7

 

8

 

9

10

11

A

 

 

 

 

 

NC/72M

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CQ

R/W

 

 

BWS1

 

K

NC/144M

 

LD

A

NC/36M

CQ

B

 

 

NC

DQ9

NC

A

NC/288M

 

K

 

 

0

 

A

NC

NC

DQ8

 

 

 

BWS

 

C

 

 

NC

NC

NC

VSS

 

A

A0

 

A

VSS

NC

DQ7

NC

D

 

 

NC

NC

DQ10

VSS

 

VSS

VSS

 

VSS

VSS

NC

NC

NC

E

 

 

NC

NC

DQ11

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

NC

DQ6

F

 

 

NC

DQ12

NC

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

DQ5

G

 

 

NC

NC

DQ13

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

NC

H

 

 

 

 

 

VREF

VDDQ

VDDQ

 

VDD

VSS

 

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

 

 

J

 

 

NC

NC

NC

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

DQ4

NC

K

 

 

NC

NC

DQ14

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

DQ3

L

 

 

NC

DQ15

NC

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

NC

DQ2

M

 

 

NC

NC

NC

VSS

 

VSS

VSS

 

VSS

VSS

NC

DQ1

NC

N

 

 

NC

NC

DQ16

VSS

 

A

 

A

 

A

VSS

NC

NC

NC

P

 

 

NC

NC

DQ17

A

 

A

C

 

A

 

A

NC

NC

DQ0

R

 

TDO

TCK

A

A

 

A

 

 

 

 

A

 

A

A

TMS

TDI

 

 

 

C

 

 

CY7C1320CV18 (512K x 36)

 

 

1

 

 

2

3

4

 

 

5

 

6

 

 

7

 

8

 

9

10

11

A

 

 

 

 

 

NC/144M

NC/36M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CQ

R/W

 

 

BWS2

 

K

 

BWS1

 

LD

A

NC/72M

CQ

B

 

 

NC

DQ27

DQ18

A

 

 

3

 

K

 

 

0

 

A

NC

NC

DQ8

 

BWS

 

BWS

 

C

 

 

NC

NC

DQ28

VSS

 

A

A0

 

A

VSS

NC

DQ17

DQ7

D

 

 

NC

DQ29

DQ19

VSS

 

VSS

VSS

 

VSS

VSS

NC

NC

DQ16

E

 

 

NC

NC

DQ20

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

DQ15

DQ6

F

 

 

NC

DQ30

DQ21

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

DQ5

G

 

 

NC

DQ31

DQ22

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

DQ14

H

 

 

 

 

 

VREF

VDDQ

VDDQ

 

VDD

VSS

 

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

 

 

NC

NC

DQ32

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

DQ13

DQ4

K

 

 

NC

NC

DQ23

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

DQ12

DQ3

L

 

 

NC

DQ33

DQ24

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

NC

DQ2

M

 

 

NC

NC

DQ34

VSS

 

VSS

VSS

 

VSS

VSS

NC

DQ11

DQ1

N

 

 

NC

DQ35

DQ25

VSS

 

A

 

A

 

A

VSS

NC

NC

DQ10

P

 

 

NC

NC

DQ26

A

 

A

C

 

A

 

A

NC

DQ9

DQ0

R

 

TDO

TCK

A

A

 

A

 

 

 

 

A

 

A

A

TMS

TDI

 

 

C

 

Note

1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 001-07160 Rev. *F

Page 3 of 26

[+] Feedback

Image 3
Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1320CV18 Logic Block Diagram CY7C1318CV18CY7C1320CV18 512K x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1318CV18 1M xReferenced with Respect to Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. WhenTCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview SRAM#1 ZQ Application ExampleProgrammable Impedance Echo ClocksComments Write Cycle DescriptionsOperation First Address External Second Address InternalDevice. D80 and D3518 remains unaltered Write cycle description table for CY7C1320CV18 follows.2Device Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence in DDR II Sram Power Up SequenceDLL Constraints Maximum Ratings Neutron Soft Error ImmunityElectrical Characteristics DC Electrical CharacteristicsParameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal ResistanceParameter Min Max DLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence26, 27 Switching WaveformsOrdering Information CY7C1320CV18-267BZXCCY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History Worldwide Sales and Design Support Products Sales, Solutions, and Legal Information