Cypress CY7C1318CV18-250BZXC Write cycle description table for CY7C1320CV18 follows.2, Device

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CY7C1318CV18

CY7C1320CV18

Write Cycle Descriptions

The write cycle description table for CY7C1320CV18 follows.[2, 8]

 

BWS0

 

BWS1

 

BWS2

 

BWS3

K

 

K

Comments

 

L

 

L

 

L

 

L

L–H

 

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

 

L

 

L

L–H

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

H

 

H

 

H

L–H

 

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

L

 

H

 

H

 

H

L–H

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

H

 

L

 

H

 

H

L–H

 

During the data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

L

 

H

 

H

L–H

During the data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

H

 

L

 

H

L–H

 

During the data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

L

 

H

L–H

During the data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

H

 

L

L–H

 

During the data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

L

L–H

During the data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

H

L–H

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

H

 

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document Number: 001-07160 Rev. *F

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1320CV18 Logic Block Diagram CY7C1318CV18Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1318CV18 1M x CY7C1320CV18 512K xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Referenced with Respect toPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Programmable Impedance Application ExampleEcho Clocks SRAM#1 ZQOperation Write Cycle DescriptionsFirst Address External Second Address Internal CommentsDevice Write cycle description table for CY7C1320CV18 follows.2Into the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence in DDR II Sram Power Up SequenceDLL Constraints Electrical Characteristics Neutron Soft Error ImmunityDC Electrical Characteristics Maximum RatingsCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max DLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence26, 27 Switching WaveformsOrdering Information CY7C1320CV18-267BZXCCY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History Worldwide Sales and Design Support Products Sales, Solutions, and Legal Information