Cypress CY7C1320CV18-267BZXC TAP AC Switching Characteristics, TAP Timing and Test Conditions

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CY7C1318CV18

CY7C1320CV18

TAP AC Switching Characteristics

Over the Operating Range[13, 14]

Parameter

Description

Min

Max

Unit

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH

20

 

ns

tTL

TCK Clock LOW

20

 

ns

Setup Times

 

 

 

 

 

 

 

 

 

tTMSS

TMS Setup to TCK Clock Rise

5

 

ns

tTDIS

TDI Setup to TCK Clock Rise

5

 

ns

tCS

Capture Setup to TCK Rise

5

 

ns

Hold Times

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Output Times

 

 

 

 

 

 

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test conditions.[14]

Figure 2. TAP Timing and Test Conditions

 

 

 

0.9V

 

 

 

 

 

 

50Ω

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

Z0

= 50Ω

 

 

 

CL = 20 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES

1.8V

0.9V

0V

(a)GND

Test Clock

TCK

Test Mode Select

TMS

Test Data In

TDI

Test Data Out

TDO

tTH

tTMSS

tTDIS

tTL

tTMSH tTCYC

tTDIH

tTDOV

 

 

 

t

 

 

 

 

 

 

 

 

TDOX

Notes

13.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

14.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Document Number: 001-07160 Rev. *F

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1318CV18 Logic Block Diagram CY7C1320CV18CY7C1318CV18 1M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1320CV18 512K xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Referenced with Respect toTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Echo Clocks Application ExampleProgrammable Impedance SRAM#1 ZQFirst Address External Second Address Internal Write Cycle DescriptionsOperation CommentsInto the device. D359 remains unaltered Write cycle description table for CY7C1320CV18 follows.2Device Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows.9TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in DDR II SramPower Up Sequence DC Electrical Characteristics Neutron Soft Error ImmunityElectrical Characteristics Maximum RatingsThermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms Read/Write/Deselect Sequence26, 27CY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Ordering InformationCY7C1320CV18-267BZXC Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products