Cypress CY7C1318CV18-200BZXC, CY7C1320CV18-200BZC, CY7C1320CV18-250BZC, 001-07160 Parameter Min Max

Page 20

CY7C1318CV18

CY7C1320CV18

Switching Characteristics

Over the Operating Range[20, 21]

 

Cypress

Consortium

 

 

 

 

 

 

Description

267 MHz

250 MHz

200 MHz

167 MHz

Unit

Parameter

Parameter

 

 

 

 

 

 

Min

Max

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

POWER

 

V (Typical) to the First Access [22]

1

–

1

–

1

–

1

–

ms

 

 

DD

 

 

 

 

 

 

 

 

 

tCYC

tKHKH

K Clock and C Clock Cycle Time

3.75

8.4

4.0

8.4

5.0

8.4

6.0

8.4

ns

tKH

tKHKL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Clock (K/K

and C/C) HIGH

1.5

–

1.6

–

2.0

–

2.4

–

ns

tKL

tKLKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Clock (K/K

and C/C) LOW

1.5

–

1.6

–

2.0

–

2.4

–

ns

tKHKH

tKHKH

K Clock Rise to

 

 

Clock Rise and C to

 

 

 

Rise

1.68

–

1.8

–

2.2

–

2.7

–

ns

K

C

 

 

 

(rising edge to rising edge)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKHCH

tKHCH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K/K

Clock Rise to C/C Clock Rise

0.00

1.68

0.00

1.8

0.00

2.2

0.00

2.7

ns

 

 

 

(rising edge to rising edge)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

tAVKH

Address Setup to K Clock Rise

0.3

–

0.5

–

0.6

–

0.7

–

ns

tSC

tIVKH

Control Setup to K Clock Rise

 

 

 

 

 

 

 

 

 

 

 

 

 

0.3

–

0.5

–

0.6

–

0.7

–

ns

(LD,

R/W)

tSCDDR

tIVKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.3

–

0.35

–

0.4

–

0.5

–

ns

Double Data Rate Control Setup to Clock (K/K)

 

 

 

 

 

Rise (BWS0, BWS1, BWS2, BWS3)

 

 

 

 

 

 

 

 

 

tSD

tDVKH

D[X:0] Setup to Clock (K and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.3

–

0.35

–

0.4

–

0.5

–

ns

K) Rise

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHA

tKHAX

Address Hold after K Clock Rise

0.3

–

0.5

–

0.6

–

0.7

–

ns

tHC

tKHIX

Control Hold after K Clock Rise

 

 

 

 

 

 

 

 

 

 

 

0.3

–

0.5

–

0.6

–

0.7

–

ns

(LD,

R/W)

tHCDDR

tKHIX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.3

–

0.35

–

0.4

–

0.5

–

ns

Double Data Rate Control Hold after Clock (K/K)

 

 

 

Rise (BWS0, BWS1, BWS2, BWS3)

 

 

 

 

 

 

 

 

 

tHD

tKHDX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D[X:0] Hold after Clock (K/K)

Rise

0.3

–

0.35

–

0.4

–

0.5

–

ns

Notes

21.When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.

22.This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD minimum initially before a read or write operation can be initiated.

Document Number: 001-07160 Rev. *F

Page 20 of 26

[+] Feedback

Page 19 Page 21
Image 20
Page 19 Page 21
Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1318CV18 Logic Block Diagram CY7C1320CV18Pin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutCY7C1318CV18 1M x CY7C1320CV18 512K xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Referenced with Respect toPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Application Example Programmable ImpedanceEcho Clocks SRAM#1 ZQWrite Cycle Descriptions OperationFirst Address External Second Address Internal CommentsWrite cycle description table for CY7C1320CV18 follows.2 DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows.9TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in DDR II SramPower Up Sequence Neutron Soft Error Immunity Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsAC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms Read/Write/Deselect Sequence26, 27CY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Ordering InformationCY7C1320CV18-267BZXC Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products
Top Page Image Contents