Cypress CY7C1320CV18-250BZC, CY7C1320CV18-200BZC, CY7C1320CV18-267BZXC, 001-07160 Document History

Page 25

CY7C1318CV18

CY7C1320CV18

Document History Page

Document Title: CY7C1318CV18/CY7C1320CV18, 18-Mbit DDR II SRAM 2-Word Burst Architecture

Document Number: 001-07160

Rev.

ECN No.

Submission

Orig. of

Description of Change

 

 

Date

Change

 

**

433284

See ECN

NXR

New data sheet

 

 

 

 

 

*A

462615

See ECN

NXR

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH

 

 

 

 

from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching

 

 

 

 

Characteristics table

 

 

 

 

Modified Power-Up waveform

*B

503690

See ECN

VKN

Minor change: Moved data sheet to web

 

 

 

 

 

*C

1523383

See ECN

VKN/AESA

Converted from preliminary to final

 

 

 

 

Updated Logic Block diagram

 

 

 

 

Removed 300 MHz and 278 MHz speed bins

 

 

 

 

Added 267 MHz speed bin

 

 

 

 

Updated IDD/ISB specs

 

 

 

 

Changed DLL minimum operating frequency from 80MHz to 120MHz

 

 

 

 

Changed tCYC max spec to 8.4ns

 

 

 

 

Modified footnotes 20 and 28

*D

2507747

See ECN

VKN/PYRS

Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to “–55°C

 

 

 

 

to +125°C” in the “Maximum Ratings“ on page 20

 

 

 

 

Updated power up sequence waveform and its description

 

 

 

 

Added footnote #19 related to IDD

 

 

 

 

Changed ΘJA spec from 28.51 to 18.7; Changed ΘJC spec from 5.91 to 4.5

*E

2518624

See ECN

NXR/PYRS

Changed JTAG ID (31:29) from 001 to 000

 

 

 

 

 

*F

2755838

08/25/2009

VKN/AESA

Removed x8 and x9 part number details

 

 

 

 

Included Soft Error Immunity Data

 

 

 

 

Modified Ordering Information table by including parts that are available and modified

 

 

 

 

the disclaimer for the Ordering information.

Document Number: 001-07160 Rev. *F

Page 25 of 26

[+] Feedback

Image 25
Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1320CV18 Logic Block Diagram CY7C1318CV18Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1318CV18 1M x CY7C1320CV18 512K xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Referenced with Respect toPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Programmable Impedance Application ExampleEcho Clocks SRAM#1 ZQOperation Write Cycle DescriptionsFirst Address External Second Address Internal CommentsDevice Write cycle description table for CY7C1320CV18 follows.2Into the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR II SramDLL Constraints Electrical Characteristics Neutron Soft Error ImmunityDC Electrical Characteristics Maximum RatingsCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max DLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence26, 27 Switching WaveformsCY7C1320CV18-267BZXC Ordering InformationCY7C1320CV18-167BZC Document Number 001-07160 Rev. *F Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History Worldwide Sales and Design Support Products Sales, Solutions, and Legal Information