Cypress CY7C1317CV18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1317CV18, CY7C1917CV18

CY7C1319CV18, CY7C1321CV18

Identification Register Definitions

	Instruction Field		Value			Description
	Instruction Field	CY7C1317CV18	CY7C1917CV18	CY7C1319CV18	CY7C1321CV18	Description
		CY7C1317CV18	CY7C1917CV18	CY7C1319CV18	CY7C1321CV18
	Revision Number	000	000	000	000	Version number.
	(31:29)
	Cypress Device ID	11010100011000101	11010100011001101	11010100011010101	11010100011100101	Defines the type of
	(28:12)					SRAM.
	Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Allows unique
	(11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an ID
						register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	107

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input and output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and TDO.
		This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input and output contents. Places the boundary scan register between TDI and
		TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input and output ring contents. Places the boundary scan register between TDI
		and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operation.

Document Number: 001-07161 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1317CV18Logic Block Diagram CY7C1917CV18 CLKLogic Block Diagram CY7C1319CV18 Logic Block Diagram CY7C1321CV18BWS CY7C1317CV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1917CV18 2M xCY7C1319CV18 1M x CY7C1321CV18 512K xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Referenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Depth Expansion Programmable ImpedanceEcho Clocks SRAM#2 Application ExampleSRAM#1 ZQ OperationWrite Cycle Descriptions CommentsInto the device. D359 remains unaltered Write cycle description table for CY7C1321CV18 followsDevice Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document Number 001-07161 Rev. *D Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms DON’T Care UndefinedOrdering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions