Cypress CY7C1317CV18, CY7C1321CV18, CY7C1319CV18 manual Switching Waveforms, DON’T Care Undefined

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CY7C1317CV18, CY7C1917CV18

CY7C1319CV18, CY7C1321CV18

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [27, 28, 29]

NOP

READ

 

 

READ

 

 

 

NOP

 

NOP

WRITE

 

 

WRITE

 

 

READ

 

 

(burst of 4)

 

(burst of 4)

 

 

 

 

 

 

 

(burst of 4)

 

(burst of 4)

 

(burst of 4)

1

2

 

 

3

4

 

5

 

 

6

 

7

 

8

9

 

10

 

11

 

12

 

13

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKH

tKL tCYC

 

tKHKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSC tHC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

A0

 

 

 

A1

 

 

 

 

 

 

 

 

A2

 

 

A3

 

 

 

A4

 

 

 

tSA tHA

 

 

 

 

 

 

 

 

 

 

 

tHD

 

 

tHD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSD

 

 

tSD

 

 

 

 

 

 

DQ

 

 

 

 

Q00

Q01

Q02

Q03

Q10

Q11

Q12

Q13

 

D20

D21

D22

D23

D30

D31

D32

D33

Q40

 

t

KHCH

 

tCLZ

 

 

 

t

CO

 

tCQD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDOH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCQDOH

 

 

 

 

 

 

 

 

 

 

 

tKHCH

 

 

 

 

 

 

 

 

 

 

 

 

 

tCHZ

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKH tKL

tCYC

tKHKH

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCQOH

 

tCCQO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

CQOH

tCCQO

 

 

 

 

 

 

 

 

 

tCQH

 

tCQHCQH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DON’T CARE

UNDEFINED

Notes

27.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

28.Outputs are disabled (High-Z) one clock cycle after a NOP.

29.In this example, if address A4 = A3, then data Q40 = D30, Q41 = D31, Q42 = D32, and Q43 = D43. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-07161 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1317CV18Logic Block Diagram CY7C1917CV18 CLKBWS Logic Block Diagram CY7C1319CV18Logic Block Diagram CY7C1321CV18 CY7C1317CV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1917CV18 2M xCY7C1319CV18 1M x CY7C1321CV18 512K xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Referenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Echo Clocks Depth ExpansionProgrammable Impedance SRAM#2 Application ExampleSRAM#1 ZQ OperationWrite Cycle Descriptions CommentsInto the device. D359 remains unaltered Write cycle description table for CY7C1321CV18 followsDevice Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document Number 001-07161 Rev. *D AC Electrical CharacteristicsInput High Voltage Vref + Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms DON’T Care UndefinedOrdering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions

CY7C1321CV18, CY7C1917CV18, CY7C1319CV18, CY7C1317CV18 specifications

Cypress Semiconductor Corporation, a leading provider of advanced embedded memory solutions, offers a series of high-performance SRAM (Static Random Access Memory) devices ideal for a variety of applications. Among these devices are the CY7C1317CV18, CY7C1319CV18, CY7C1917CV18, and CY7C1321CV18. These components are designed to meet the growing demands for non-volatile memory in consumer electronics, automotive systems, telecommunications, and industrial applications.

The CY7C1317CV18 and CY7C1319CV18 are both 256K-bit static RAMs with distinct features. The CY7C1317CV18 offers a dual-port architecture, enabling concurrent access from multiple sources, which substantially enhances performance in data-intensive applications. On the other hand, the CY7C1319CV18 is designed for single-port access, making it ideal for simpler applications that do not require simultaneous data reads and writes.

Further extending Cypress's SRAM portfolio, the CY7C1917CV18 provides a 2M-bit memory configuration with fast access times, high-density storage, and low power consumption. It is particularly well-suited for applications needing quick data retrieval while maintaining efficiency. The architecture of the CY7C1917CV18 allows it to be integrated seamlessly into systems requiring reliable and robust data storage.

Completing the lineup is the CY7C1321CV18, which features an innovative 1M-bit SRAM design. This SRAM is known for its low latency and high speed, making it an excellent choice for high-performance computing applications. It supports a wide operating voltage range and provides a reliable solution for volatile memory needs, especially in fast caching scenarios.

These SRAM devices utilize advanced CMOS technology to achieve high speed and low power characteristics, making them competitive choices in the market. Their robust performance ensures that they satisfy the stringent requirements of various applications, including high-speed networking, graphics processing, and instrumentation.

In terms of reliability, all four devices are built to endure challenging operating conditions and provide excellent data retention. They are offered in compact packages that facilitate easy integration into PCBs, optimizing space and enhancing design flexibility. The combination of performance, low power consumption, and scalability makes Cypress's SRAM products particularly advantageous for next-generation applications across multiple industries.