Cypress CY7C1917CV18, CY7C1321CV18, CY7C1319CV18 manual Sales, Solutions, and Legal Information

Page 31

CY7C1317CV18, CY7C1917CV18

CY7C1319CV18, CY7C1321CV18

Document History Page

Document Title: CY7C1317CV18/CY7C1917CV18/CY7C1319CV18/CY7C1321CV18, 18-Mbit DDR-II SRAM 4-Word

Burst Architecture

Document Number: 001-07161

Rev.

ECN No.

Submission

Orig. of

Description of Change

 

 

Date

Change

 

**

433284

See ECN

NXR

New Data Sheet

 

 

 

 

 

*A

462615

See ECN

NXR

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH,

 

 

 

 

tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching

 

 

 

 

Characteristics table

 

 

 

 

Modified Power-Up waveform

*B

1523383

See ECN

VKN/AESA

Converted from preliminary to final

 

 

 

 

Updated Logic Block diagram

 

 

 

 

Updated IDD/ISB specs

 

 

 

 

Changed DLL minimum operating frequency from 80MHz to 120MHz

 

 

 

 

Changed tCYC max spec to 8.4ns

 

 

 

 

Modified Switching waveform

 

 

 

 

Modified footnotes 20 and 28

*C

2507747

See ECN

VKN/PYRS

Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to

 

 

 

 

“–55°C to +125°C” in the “Maximum Ratings“ on page 21

 

 

 

 

Updated power up sequence waveform and its description

 

 

 

 

Added footnote #19 related to IDD

 

 

 

 

Changed ΘJA spec from 28.51 to 18.7

 

 

 

 

Changed ΘJC spec from 5.91 to 4.5

*D

2518624

See ECN

NXR/PYRS

Changed JTAG ID (31:29) from 001 to 000

 

 

 

 

 

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© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-07161 Rev. *D

Revised June 18, 2008

Page 31 of 31

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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Contents Selection Guide FeaturesConfigurations Functional DescriptionCLK Logic Block Diagram CY7C1317CV18Logic Block Diagram CY7C1917CV18 DoffLogic Block Diagram CY7C1321CV18 Logic Block Diagram CY7C1319CV18BWS CY7C1917CV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1317CV18 2M xCY7C1321CV18 512K x CY7C1319CV18 1M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toFunctional Overview Programmable Impedance Depth ExpansionEcho Clocks Operation Application ExampleSRAM#1 ZQ SRAM#2Comments Write Cycle DescriptionsDevice. D80 and D3518 remains unaltered Write cycle description table for CY7C1321CV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Input High Voltage Vref + AC Electrical CharacteristicsInput LOW Voltage Vref Document Number 001-07161 Rev. *D Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max DLL Timing Parameter Min Max Output TimesDON’T Care Undefined Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information

CY7C1321CV18, CY7C1917CV18, CY7C1319CV18, CY7C1317CV18 specifications

Cypress Semiconductor Corporation, a leading provider of advanced embedded memory solutions, offers a series of high-performance SRAM (Static Random Access Memory) devices ideal for a variety of applications. Among these devices are the CY7C1317CV18, CY7C1319CV18, CY7C1917CV18, and CY7C1321CV18. These components are designed to meet the growing demands for non-volatile memory in consumer electronics, automotive systems, telecommunications, and industrial applications.

The CY7C1317CV18 and CY7C1319CV18 are both 256K-bit static RAMs with distinct features. The CY7C1317CV18 offers a dual-port architecture, enabling concurrent access from multiple sources, which substantially enhances performance in data-intensive applications. On the other hand, the CY7C1319CV18 is designed for single-port access, making it ideal for simpler applications that do not require simultaneous data reads and writes.

Further extending Cypress's SRAM portfolio, the CY7C1917CV18 provides a 2M-bit memory configuration with fast access times, high-density storage, and low power consumption. It is particularly well-suited for applications needing quick data retrieval while maintaining efficiency. The architecture of the CY7C1917CV18 allows it to be integrated seamlessly into systems requiring reliable and robust data storage.

Completing the lineup is the CY7C1321CV18, which features an innovative 1M-bit SRAM design. This SRAM is known for its low latency and high speed, making it an excellent choice for high-performance computing applications. It supports a wide operating voltage range and provides a reliable solution for volatile memory needs, especially in fast caching scenarios.

These SRAM devices utilize advanced CMOS technology to achieve high speed and low power characteristics, making them competitive choices in the market. Their robust performance ensures that they satisfy the stringent requirements of various applications, including high-speed networking, graphics processing, and instrumentation.

In terms of reliability, all four devices are built to endure challenging operating conditions and provide excellent data retention. They are offered in compact packages that facilitate easy integration into PCBs, optimizing space and enhancing design flexibility. The combination of performance, low power consumption, and scalability makes Cypress's SRAM products particularly advantageous for next-generation applications across multiple industries.
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