Cypress CY7C1319CV18, CY7C1321CV18, CY7C1317CV18, CY7C1917CV18 manual 167

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CY7C1317CV18, CY7C1917CV18

CY7C1319CV18, CY7C1321CV18

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
167	CY7C1317CV18-167BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1917CV18-167BZC

	CY7C1319CV18-167BZC

	CY7C1321CV18-167BZC

	CY7C1317CV18-167BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1917CV18-167BZXC

	CY7C1319CV18-167BZXC

	CY7C1321CV18-167BZXC

	CY7C1317CV18-167BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1917CV18-167BZI

	CY7C1319CV18-167BZI

	CY7C1321CV18-167BZI

	CY7C1317CV18-167BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1917CV18-167BZXI

	CY7C1319CV18-167BZXI

	CY7C1321CV18-167BZXI

Document Number: 001-07161 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1917CV18 Logic Block Diagram CY7C1317CV18Doff CLKBWS Logic Block Diagram CY7C1319CV18Logic Block Diagram CY7C1321CV18 Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1317CV18 2M x CY7C1917CV18 2M xCY7C1321CV18 512K x CY7C1319CV18 1M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Echo Clocks Depth ExpansionProgrammable Impedance SRAM#1 ZQ Application ExampleSRAM#2 OperationComments Write Cycle DescriptionsDevice Write cycle description table for CY7C1321CV18 followsInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document Number 001-07161 Rev. *D AC Electrical CharacteristicsInput High Voltage Vref + Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max DLL Timing Parameter Min Max Output Times DON’T Care Undefined Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information