Cypress CY7C1917CV18, CY7C1321CV18, CY7C1319CV18, CY7C1317CV18 Write Cycle Descriptions, Comments

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CY7C1317CV18, CY7C1917CV18

CY7C1319CV18, CY7C1321CV18

Burst Address Table

(CY7C1319CV18, CY7C1321CV18)

First Address (External)

Second Address (Internal)

Third Address (Internal)

Fourth Address (Internal)

X..X00

X..X01

X..X10

X..X11

 

 

 

 

X..X01

X..X10

X..X11

X..X00

 

 

 

 

X..X10

X..X11

X..X00

X..X01

 

 

 

 

X..X11

X..X00

X..X01

X..X10

 

 

 

 

Write Cycle Descriptions

The write cycle description table for CY7C1317CV18 and CY7C1319CV18 follows. [2, 8]

 

BWS0/

BWS1/

K

 

 

 

Comments

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

NWS0

 

NWS1

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

L–H

 

–

During the data portion of a write sequence :

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1317CV18 − both nibbles (D[7:0]) are written into the device,

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1319CV18 − both bytes (D[17:0]) are written into the device.

 

 

 

L

 

L

–

L-H

During the data portion of a write sequence :

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1317CV18 − both nibbles (D[7:0]) are written into the device,

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1319CV18 − both bytes (D[17:0]) are written into the device.

 

 

 

L

 

H

L–H

 

–

During the data portion of a write sequence :

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1317CV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1319CV18 − only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

L

 

H

–

L–H

During the data portion of a write sequence :

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1317CV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1319CV18 − only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

H

 

L

L–H

 

–

During the data portion of a write sequence :

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1317CV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1319CV18 − only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

H

 

L

–

L–H

During the data portion of a write sequence :

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1317CV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1319CV18 − only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

H

 

H

L–H

 

–

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

–

L–H

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle Descriptions

The write cycle description table for CY7C1917CV18 follows. [2, 8]

BWS0

K

K

Comments

L

L–H

–

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

L

–

L–H

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

H

L–H

–

No data is written into the device during this portion of a write operation.

 

 

 

 

H

–

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

Note

8.Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.

Document Number: 001-07161 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionCLK Logic Block Diagram CY7C1317CV18Logic Block Diagram CY7C1917CV18 DoffBWS Logic Block Diagram CY7C1319CV18Logic Block Diagram CY7C1321CV18 CY7C1917CV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1317CV18 2M xCY7C1321CV18 512K x CY7C1319CV18 1M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toFunctional Overview Echo Clocks Depth ExpansionProgrammable Impedance Operation Application ExampleSRAM#1 ZQ SRAM#2Comments Write Cycle DescriptionsDevice. D80 and D3518 remains unaltered Write cycle description table for CY7C1321CV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document Number 001-07161 Rev. *D AC Electrical CharacteristicsInput High Voltage Vref + Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max DLL Timing Parameter Min Max Output TimesDON’T Care Undefined Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information

CY7C1321CV18, CY7C1917CV18, CY7C1319CV18, CY7C1317CV18 specifications

Cypress Semiconductor Corporation, a leading provider of advanced embedded memory solutions, offers a series of high-performance SRAM (Static Random Access Memory) devices ideal for a variety of applications. Among these devices are the CY7C1317CV18, CY7C1319CV18, CY7C1917CV18, and CY7C1321CV18. These components are designed to meet the growing demands for non-volatile memory in consumer electronics, automotive systems, telecommunications, and industrial applications.

The CY7C1317CV18 and CY7C1319CV18 are both 256K-bit static RAMs with distinct features. The CY7C1317CV18 offers a dual-port architecture, enabling concurrent access from multiple sources, which substantially enhances performance in data-intensive applications. On the other hand, the CY7C1319CV18 is designed for single-port access, making it ideal for simpler applications that do not require simultaneous data reads and writes.

Further extending Cypress's SRAM portfolio, the CY7C1917CV18 provides a 2M-bit memory configuration with fast access times, high-density storage, and low power consumption. It is particularly well-suited for applications needing quick data retrieval while maintaining efficiency. The architecture of the CY7C1917CV18 allows it to be integrated seamlessly into systems requiring reliable and robust data storage.

Completing the lineup is the CY7C1321CV18, which features an innovative 1M-bit SRAM design. This SRAM is known for its low latency and high speed, making it an excellent choice for high-performance computing applications. It supports a wide operating voltage range and provides a reliable solution for volatile memory needs, especially in fast caching scenarios.

These SRAM devices utilize advanced CMOS technology to achieve high speed and low power characteristics, making them competitive choices in the market. Their robust performance ensures that they satisfy the stringent requirements of various applications, including high-speed networking, graphics processing, and instrumentation.

In terms of reliability, all four devices are built to endure challenging operating conditions and provide excellent data retention. They are offered in compact packages that facilitate easy integration into PCBs, optimizing space and enhancing design flexibility. The combination of performance, low power consumption, and scalability makes Cypress's SRAM products particularly advantageous for next-generation applications across multiple industries.
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