Cypress CY7C1317CV18, CY7C1917CV18 manual CY7C1319CV18 1M x, CY7C1321CV18 512K x

Page 5

CY7C1317CV18, CY7C1917CV18

CY7C1319CV18, CY7C1321CV18

Pin Configuration (continued)

The pin configuration for CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follow. [1]

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1319CV18 (1M x 18)

 

 

1

 

 

2

3

4

 

5

 

6

 

7

 

8

 

9

10

11

A

 

 

 

 

 

NC/72M

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CQ

R/W

 

 

BWS1

 

K

NC/144M

 

LD

A

NC/36M

CQ

B

 

 

NC

DQ9

NC

A

NC/288M

 

K

 

 

0

 

A

NC

NC

DQ8

 

 

 

BWS

 

C

 

 

NC

NC

NC

VSS

 

A

A0

 

A1

VSS

NC

DQ7

NC

D

 

 

NC

NC

DQ10

VSS

 

VSS

VSS

 

VSS

VSS

NC

NC

NC

E

 

 

NC

NC

DQ11

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

NC

DQ6

F

 

 

NC

DQ12

NC

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

DQ5

G

 

 

NC

NC

DQ13

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

NC

H

 

 

 

 

 

VREF

VDDQ

VDDQ

 

VDD

VSS

 

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

 

 

J

 

 

NC

NC

NC

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

DQ4

NC

K

 

 

NC

NC

DQ14

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

DQ3

L

 

 

NC

DQ15

NC

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

NC

DQ2

M

 

 

NC

NC

NC

VSS

 

VSS

VSS

 

VSS

VSS

NC

DQ1

NC

N

 

 

NC

NC

DQ16

VSS

 

A

 

A

 

A

VSS

NC

NC

NC

P

 

 

NC

NC

DQ17

A

 

A

C

 

A

 

A

NC

NC

DQ0

R

 

TDO

TCK

A

A

 

A

 

 

 

 

A

 

A

A

TMS

TDI

 

 

 

C

 

 

CY7C1321CV18 (512K x 36)

 

 

1

 

 

2

3

4

 

 

5

 

6

 

 

7

 

8

 

9

10

11

A

 

 

 

 

 

NC/144M

NC/36M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CQ

R/W

 

 

BWS2

 

K

 

BWS1

 

LD

A

NC/72M

CQ

B

 

 

NC

DQ27

DQ18

A

 

 

3

 

K

 

 

0

 

A

NC

NC

DQ8

 

BWS

 

BWS

 

C

 

 

NC

NC

DQ28

VSS

 

A

A0

 

A1

VSS

NC

DQ17

DQ7

D

 

 

NC

DQ29

DQ19

VSS

 

VSS

VSS

 

VSS

VSS

NC

NC

DQ16

E

 

 

NC

NC

DQ20

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

DQ15

DQ6

F

 

 

NC

DQ30

DQ21

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

DQ5

G

 

 

NC

DQ31

DQ22

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

DQ14

H

 

 

 

 

 

VREF

VDDQ

VDDQ

 

VDD

VSS

 

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

 

 

NC

NC

DQ32

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

DQ13

DQ4

K

 

 

NC

NC

DQ23

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

DQ12

DQ3

L

 

 

NC

DQ33

DQ24

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

NC

DQ2

M

 

 

NC

NC

DQ34

VSS

 

VSS

VSS

 

VSS

VSS

NC

DQ11

DQ1

N

 

 

NC

DQ35

DQ25

VSS

 

A

 

A

 

A

VSS

NC

NC

DQ10

P

 

 

NC

NC

DQ26

A

 

A

C

 

A

 

A

NC

DQ9

DQ0

R

 

TDO

TCK

A

A

 

A

 

 

 

 

A

 

A

A

TMS

TDI

 

 

C

 

Document Number: 001-07161 Rev. *D

Page 5 of 31

[+] Feedback

Image 5
Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1917CV18 Logic Block Diagram CY7C1317CV18Doff CLKBWS Logic Block Diagram CY7C1319CV18Logic Block Diagram CY7C1321CV18 Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1317CV18 2M x CY7C1917CV18 2M xCY7C1321CV18 512K x CY7C1319CV18 1M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Echo Clocks Depth ExpansionProgrammable Impedance SRAM#1 ZQ Application ExampleSRAM#2 OperationComments Write Cycle DescriptionsDevice Write cycle description table for CY7C1321CV18 followsInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document Number 001-07161 Rev. *D AC Electrical CharacteristicsInput High Voltage Vref + Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max DLL Timing Parameter Min Max Output TimesDON’T Care Undefined Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information

CY7C1321CV18, CY7C1917CV18, CY7C1319CV18, CY7C1317CV18 specifications

Cypress Semiconductor Corporation, a leading provider of advanced embedded memory solutions, offers a series of high-performance SRAM (Static Random Access Memory) devices ideal for a variety of applications. Among these devices are the CY7C1317CV18, CY7C1319CV18, CY7C1917CV18, and CY7C1321CV18. These components are designed to meet the growing demands for non-volatile memory in consumer electronics, automotive systems, telecommunications, and industrial applications.

The CY7C1317CV18 and CY7C1319CV18 are both 256K-bit static RAMs with distinct features. The CY7C1317CV18 offers a dual-port architecture, enabling concurrent access from multiple sources, which substantially enhances performance in data-intensive applications. On the other hand, the CY7C1319CV18 is designed for single-port access, making it ideal for simpler applications that do not require simultaneous data reads and writes.

Further extending Cypress's SRAM portfolio, the CY7C1917CV18 provides a 2M-bit memory configuration with fast access times, high-density storage, and low power consumption. It is particularly well-suited for applications needing quick data retrieval while maintaining efficiency. The architecture of the CY7C1917CV18 allows it to be integrated seamlessly into systems requiring reliable and robust data storage.

Completing the lineup is the CY7C1321CV18, which features an innovative 1M-bit SRAM design. This SRAM is known for its low latency and high speed, making it an excellent choice for high-performance computing applications. It supports a wide operating voltage range and provides a reliable solution for volatile memory needs, especially in fast caching scenarios.

These SRAM devices utilize advanced CMOS technology to achieve high speed and low power characteristics, making them competitive choices in the market. Their robust performance ensures that they satisfy the stringent requirements of various applications, including high-speed networking, graphics processing, and instrumentation.

In terms of reliability, all four devices are built to endure challenging operating conditions and provide excellent data retention. They are offered in compact packages that facilitate easy integration into PCBs, optimizing space and enhancing design flexibility. The combination of performance, low power consumption, and scalability makes Cypress's SRAM products particularly advantageous for next-generation applications across multiple industries.