Cypress CY7C1317CV18, CY7C1321CV18, CY7C1319CV18 manual Pin Definitions, Pin Name Pin Description

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CY7C1317CV18, CY7C1917CV18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1319CV18, CY7C1321CV18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

IO

 

 

 

 

Pin Description

 

 

DQ[x:0]

Input Output-

Data Input Output Signals. Inputs are sampled on the rising edge of K and

 

clocks during valid write

 

K

 

 

 

 

 

 

 

 

Synchronous

operations. These pins drive out the requested data during a read operation. Valid data is driven out on

 

 

 

 

 

 

 

 

 

the rising edge of both the C and C clocks during read operations or K and K when in single clock mode.

 

 

 

 

 

 

 

 

 

When read access is deselected, Q[x:0] are automatically tri-stated.

 

 

 

 

 

 

 

 

 

CY7C1317CV18 − DQ[7:0]

 

 

 

 

 

 

 

 

 

CY7C1917CV18 − DQ[8:0]

 

 

 

 

 

 

 

 

 

CY7C1319CV18 − DQ[17:0]

 

 

 

 

 

 

 

 

 

CY7C1321CV18 − DQ[35:0]

 

 

 

 

 

 

 

 

Input-

Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition

 

 

LD

 

 

 

 

 

 

 

 

Synchronous

includes address and read/write direction. All transactions operate on a burst of 4 data (two clock periods

 

 

 

 

 

 

 

 

 

of bus activity).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0,

Input-

Nibble Write Select 0, 1 − Active LOW (CY7C1317CV18 only). Sampled on the rising edge of the K

 

 

NWS

 

 

NWS1

Synchronous

and K clocks during write operations. Used to select which nibble is written into the device during the

 

 

 

 

 

 

 

 

 

current portion of the write operations. Nibbles not written remain unaltered.

 

 

 

 

 

 

 

 

 

NWS0 controls D[3:0] and NWS1 controls D[7:4].

 

 

 

 

 

 

 

 

 

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

 

 

 

 

 

 

 

 

 

ignores the corresponding nibble of data and it is not written into the device.

 

 

 

 

 

 

0,

Input-

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and

 

 

clocks during

 

 

BWS

K

 

 

BWS1,

Synchronous

write operations. Used to select which byte is written into the device during the current portion of the Write

 

 

BWS2,

 

operations. Bytes not written remain unaltered.

 

 

BWS3

 

CY7C1917CV18 − BWS0

controls D[8:0]

 

 

 

 

 

 

 

 

 

CY7C1319CV18 − BWS0

controls D[8:0] and

BWS

1 controls D

[17:9].

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1321CV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls

 

 

 

 

 

 

 

 

 

D[35:27].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

 

 

 

 

 

 

 

 

 

ignores the corresponding byte of data and it is not written into the device.

 

 

A, A0, A1

Input-

Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the

 

 

 

 

 

 

 

 

Synchronous

device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1317CV18 and 2M x 9 (4 arrays each

 

 

 

 

 

 

 

 

 

of 512K x 9) for CY7C1917CV18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1319CV18, and 512K

 

 

 

 

 

 

 

 

 

x 36 (4 arrays each of 128K x 36) for CY7C1321CV18.

 

 

 

 

 

 

 

 

 

CY7C1317CV18 – Because the least two significant bits of the address internally are “00”, only 19 external

 

 

 

 

 

 

 

 

 

address inputs are needed to access the entire memory array.

 

 

 

 

 

 

 

 

 

CY7C1917CV18 – Because the least two significant bits of the address internally are “00”, only 19 external

 

 

 

 

 

 

 

 

 

address inputs are needed to access the entire memory array.

 

 

 

 

 

 

 

 

 

CY7C1319CV18 – A0 and A1 are the inputs to the burst counter. These are incremented internally in a

 

 

 

 

 

 

 

 

 

linear fashion. 20 address inputs are needed to access the entire memory array.

 

 

 

 

 

 

 

 

 

CY7C1321CV18 – A0 and A1 are the inputs to the burst counter. These are incremented internally in a

 

 

 

 

 

 

 

 

 

linear fashion. 19 address inputs are needed to access the entire memory array.

 

 

 

 

 

 

Input-

Synchronous Read/Write Input. When

 

is LOW, this input designates the access type (read when

 

 

R/W

LD

 

 

 

 

 

 

 

 

Synchronous

R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times

 

 

 

 

 

 

 

 

 

around the edge of K.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CInput Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 10 for more information.

CInput Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 10 for more information.

K

Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

 

and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising

 

edge of K.

KInput Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and to drive out data through Q[x:0] when in single clock mode.

Document Number: 001-07161 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1317CV18Logic Block Diagram CY7C1917CV18 CLKLogic Block Diagram CY7C1319CV18 Logic Block Diagram CY7C1321CV18BWS CY7C1317CV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1917CV18 2M xCY7C1319CV18 1M x CY7C1321CV18 512K xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Referenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Depth Expansion Programmable ImpedanceEcho Clocks SRAM#2 Application ExampleSRAM#1 ZQ OperationWrite Cycle Descriptions CommentsInto the device. D359 remains unaltered Write cycle description table for CY7C1321CV18 followsDevice Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document Number 001-07161 Rev. *D Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms DON’T Care UndefinedOrdering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions

CY7C1321CV18, CY7C1917CV18, CY7C1319CV18, CY7C1317CV18 specifications

Cypress Semiconductor Corporation, a leading provider of advanced embedded memory solutions, offers a series of high-performance SRAM (Static Random Access Memory) devices ideal for a variety of applications. Among these devices are the CY7C1317CV18, CY7C1319CV18, CY7C1917CV18, and CY7C1321CV18. These components are designed to meet the growing demands for non-volatile memory in consumer electronics, automotive systems, telecommunications, and industrial applications.

The CY7C1317CV18 and CY7C1319CV18 are both 256K-bit static RAMs with distinct features. The CY7C1317CV18 offers a dual-port architecture, enabling concurrent access from multiple sources, which substantially enhances performance in data-intensive applications. On the other hand, the CY7C1319CV18 is designed for single-port access, making it ideal for simpler applications that do not require simultaneous data reads and writes.

Further extending Cypress's SRAM portfolio, the CY7C1917CV18 provides a 2M-bit memory configuration with fast access times, high-density storage, and low power consumption. It is particularly well-suited for applications needing quick data retrieval while maintaining efficiency. The architecture of the CY7C1917CV18 allows it to be integrated seamlessly into systems requiring reliable and robust data storage.

Completing the lineup is the CY7C1321CV18, which features an innovative 1M-bit SRAM design. This SRAM is known for its low latency and high speed, making it an excellent choice for high-performance computing applications. It supports a wide operating voltage range and provides a reliable solution for volatile memory needs, especially in fast caching scenarios.

These SRAM devices utilize advanced CMOS technology to achieve high speed and low power characteristics, making them competitive choices in the market. Their robust performance ensures that they satisfy the stringent requirements of various applications, including high-speed networking, graphics processing, and instrumentation.

In terms of reliability, all four devices are built to endure challenging operating conditions and provide excellent data retention. They are offered in compact packages that facilitate easy integration into PCBs, optimizing space and enhancing design flexibility. The combination of performance, low power consumption, and scalability makes Cypress's SRAM products particularly advantageous for next-generation applications across multiple industries.
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