Transcend Information TS32M~1GCF80 dimensions True IDE PIO Mode Read/Write Timing Specification

Page 25

TS32M~1GCF80

 

 

 

 

 

80X CompactFlash Card

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.11 True IDE PIO Mode Read/Write Timing Specification

 

 

 

 

 

 

 

 

 

 

Item

 

 

 

Mode

 

 

 

Note

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

2

3

4

5

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t0

Cycle time (min)

600

383

240

180

120

100

80

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t1

Address Valid to -IORD/-IOWR

70

50

30

30

25

15

10

 

 

 

 

 

setup (min)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t2

-IORD/-IOWR (min)

165

125

100

80

70

65

55

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t2

-IORD/-IOWR (min) Register (8 bit)

290

290

290

80

70

65

55

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t2i

-IORD/-IOWR recovery time (min)

-

-

-

70

25

25

20

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t3

-IOWR data setup (min)

60

45

30

30

20

20

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t4

-IOWR data hold (min)

30

20

15

10

10

5

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t5

-IORD data setup (min)

50

35

20

20

20

15

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t6

-IORD data hold (min)

5

5

5

5

5

5

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T6Z

-IORD data tristate (max)

30

30

30

30

30

20

20

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t7

Address valid to -IOCS16 assertion

90

50

40

n/a

n/a

n/a

n/a

4

 

 

 

 

(max)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t8

Address valid to -IOCS16 released

60

45

30

n/a

n/a

n/a

n/a

4

 

 

 

 

(max)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t9

-IORD/-IOWR to address valid hold

20

15

10

10

10

10

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRD

Read Data Valid to IORDY active

0

0

0

0

0

0

0

 

 

 

 

 

(min), if IORDY initially low after tA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tA

IORDY Setup time

35

35

35

35

35

na5

na5

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tB

IORDY Pulse Width (max)

125

1250

1250

1250

1250

na5

na5

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

tC

IORDY assertion to release (max)

5

5

5

5

5

na5

na5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below 120nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from -IORDY high to -IORD high is 0 nsec, but minimum -IORD width shall still be met.

1)t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i shall be met. The minimum total cycle time requirement is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the device’s identify device data. A CompactFlash Storage Card implementation shall support any legal host implementation.

2)This parameter specifies the time from the negation edge of -IORD to the time that the data bus is no longer driven by the CompactFlash Storage Card (tri-state).

3)The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the CompactFlash Storage Card is not driving IORDY negated at tA after the activation of -IORD or -IOWR, then t5 shall be met and tRD is not applicable. If the CompactFlash Storage Card is driving IORDY negated at the time tA after the activation of -IORD or -IOWR, then tRD shall be met and t5 is not applicable.

4)t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid.

5)IORDY is not supported in this mode.

Transcend Information Inc.

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V1.1

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Contents Dimensions Placement FeatureDescription 80X CompactFlash CardCHS and Capacity Ordering InformationCompactflash Card Specification Block Diagram Electrical Interface Pin Assignment and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode4V1.1 Signal Name Dir Pin Description Signal DescriptionCsel V1.1 Iord REG True IDE Mode As Iordy Input Leakage Current Electrical SpecificationParameter Symbol Min Max Unit Remark Input Characteristics CompactFlash interface I/O atMin Max Unit ParameterOutput Drive Type Output Drive Characteristics Signal Card Host Signal Interface150 μ a high state per socket TS32M~1GCF8080X CompactFlash CardAttribute Memory Read Timing Figure Attribute Memory Read Timing DiagramConfiguration Register Attribute Memory Write Timing Cycle Time Mode 250 ns 120 ns 100 ns 80 ns Common Memory Read Timing SpecificationMin Max Symbol Min Symbol Common Memory Write Timing Specification80X CompactFlash Card I/O Input Read Timing SpecificationCycle Time Mode 255 ns 120 ns 100 ns 80 ns 10 I/O Output Write Timing SpecificationMode True IDE PIO Mode Read/Write Timing SpecificationV1.1 True IDE Multiword DMA Mode Read/Write Timing Specification Multiple Function CompactFlash Storage Cards Card ConfigurationCE2 CE1 A10 A8-A4Attribute Memory Function Function ModeCE2 CE1 A10 D15-D8 D7-D0 Configuration Option RegisterBase + 00h in Attribute Memory Table CompactFlash Storage Card ConfigurationsTable Pin Replacement Changed Bit/Mask Bit Values Pin Replacement Register Base + 04h in Attribute MemoryI/O Transfer Function Socket and Copy Register Base + 06h in Attribute MemoryTable Pcmcia Mode I/O Function True IDE Mode I/O Transfer FunctionCommon Memory Transfer Function Function CodeV1.1 CF-ATA Drive Register Set Definition and Protocol Table I/O ConfigurationsTable Primary and Secondary I/O Decoding I/O Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing CF-ATA Registers True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 Table Data Register Access Error Register Address 1F1h171h Offset 1, 0Dh Read OnlySector Count Register Address 1F2h172h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetFigure Status & Alternate Status Register Device Control Register Address 3F6h376h Offset EhFigure Device Control Register Card Drive Address Register Address 3F7h377h Offset FhCF-ATA Command Description LBA CF-ATA Command SetDefinitions Execute Drive Diagnostic 90h Check Power Mode 98h or E5hBit Command Cyl High Cyl Low Sec Num Sec Cnt FeatureFormat Track 50h Erase Sectors C0hDrive Head LBA Cyl High Sec Num LBA Sec CntIdentify Device Ech Word Default Total Data Field Type InformationBytes Total Data Field Type Information Word 1 Default Number of Cylinders Word 0 General ConfigurationWord 3 Default Number of Heads Word 6 Default Number of Sectors per TrackPIO Data Transfer Cycle Timing Mode Word 49 Capabilities Bit 13 Standby TimerMultiple Sector Setting Total Sectors Addressable in LBA ModeWord 64 Advanced PIO transfer modes supported Multiword DMA transferWord 65 Minimum Multiword DMA transfer cycle time Recommended Multiword DMA transfer cycle timeWords 85-87 Features/command sets enabled Words 82-84 Features/command sets supportedWord 68 Minimum PIO transfer cycle time with Iordy Word 89 Time required for Security erase unit completion Word 91 Advanced power management level valueWord 128 Security Status Bit 8 Security Level Value Maximum PIO mode timing selected Word 160 Power Requirement DescriptionAdditional Requirements for CF Advanced Timing Modes Value Current PIO timing mode selected Value Maximum Multiword DMA timing mode supportedValue Current Multiword DMA timing mode selected Value Maximum Pcmcia IO timing mode SupportedIdle 97h or E3h Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureIdle Immediate 95h or E1h Initialize Drive Parameters 91hRead DMA C8h Read Buffer E4hRead Multiple C4h Read Verify Sectors 40h or 41h Read Sectors 20h or 21hRequest Sense 03h Recalibrate 1XhSeek 7Xh Table Extended Error CodesTable Feature Supported Set Features EFhSet Multiple Mode C6h Standby 96h or E2h Set Sleep Mode- 99h or E6hTranslate Sector 87h Standby Immediate 94h or E0hTableTranslate Sector Information Write Buffer E8h Wear Level F5hWrite DMA CAh Write Multiple Command C5h Write Sectors 30h or 31h Write Multiple without Erase CDhWrite Verify 3Ch Write Sectors without Erase 38hBBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR 80X CompactFlash Card Error PostingCIS Description Address Data Description of Contents CIS functionAddress Data 5 4 Description of Contents CIS function Cistplconfig V1.1 MS IR IO RO a Address Data 5 4 3 2 1 Description of Contents CIS function Irqn LS AS NR RO a T