Transcend Information TS32M~1GCF80 dimensions True IDE Mode Addressing, CF-ATA Registers

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TS32M~1GCF80

80X CompactFlash Card

 

 

 

Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory to memory block move instruction. Some PCMCIA socket adapters also have auto incrementing address logic embedded within them. This address window allows these hosts and adapters to function efficiently.

Note that this entire window accesses the Data Register FIFO and does not allow random access to the data buffer within the CompactFlash Storage Card.

A word access to address at offset 8 shall provide even data on the low-order byte of the data bus, along with odd data at offset 9 on the high-order byte of the data bus.

5.4 True IDE Mode Addressing

When the CompactFlash Storage Card is configured in the True IDE Mode, the I/O decoding is as follows:

Note: 1) See the section 6.1.5 CF-ATA Registers for information regarding the control of 8 or 16 bit transfers to the data register.

5.5 CF-ATA Registers

The following section describes the hardware registers used by the host software to issue commands to the CompactFlash device. These registers are often collectively referred to as the “task file.”

Note: In accordance with the PCMCIA specification: each of the registers below that is located at an odd offset address may be accessed in the PC Card Memory or PC Card I/O modes at its normal address and also the corresponding even address (normal address -1) using data bus lines (D15-D8) when -CE1 is high and -CE2 is low unless -IOIS16 is high (not asserted by the card) and an I/O cycle is being performed.

In the True IDE mode of operation, the size of the transfer is based solely on the register being addressed. All registers are 8 bit only except for the Data Register, which is normally 16 bits, but can be programmed to use 8 bit transfers for Non-DMA operations through the use of the Set Features command. The data register is also 8 bits during a portion of the Read Long and Write Long commands, which exist solely for historical reasons and should not be used.

5.5.1 Data Register (Address - 1F0h[170h];Offset 0,8,9)

The Data Register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash Storage Card data buffer and the Host. This register overlaps the Error Register Table: Data Register Access below describes the combinations of data register access and is provided to assist in understanding the overlapped Data Register and Error/Feature Register rather than to attempt to define general PCMCIA word and byte access modes and operations.

See the PCMCIA PC Card Standard, for further definitions of the Card Accessing Modes for I/O and Memory cycles.

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Contents 80X CompactFlash Card Placement FeatureDimensions DescriptionCHS and Capacity Ordering InformationCompactflash Card Specification Block Diagram Electrical Interface Pin Assignment and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode4V1.1 Signal Name Dir Pin Description Signal DescriptionCsel V1.1 Iord REG True IDE Mode As Iordy Input Leakage Current Electrical SpecificationParameter Symbol Min Max Unit Remark Input Characteristics CompactFlash interface I/O atMin Max Unit ParameterOutput Drive Type Output Drive Characteristics Signal Card Host Signal Interface150 μ a high state per socket TS32M~1GCF8080X CompactFlash CardAttribute Memory Read Timing Figure Attribute Memory Read Timing DiagramConfiguration Register Attribute Memory Write Timing Common Memory Read Timing Specification Cycle Time Mode 250 ns 120 ns 100 ns 80 nsMin Max Symbol Min Symbol Common Memory Write Timing Specification80X CompactFlash Card I/O Input Read Timing SpecificationCycle Time Mode 255 ns 120 ns 100 ns 80 ns 10 I/O Output Write Timing SpecificationMode True IDE PIO Mode Read/Write Timing SpecificationV1.1 True IDE Multiword DMA Mode Read/Write Timing Specification A10 A8-A4 Card ConfigurationMultiple Function CompactFlash Storage Cards CE2 CE1Function Mode Attribute Memory FunctionCE2 CE1 A10 D15-D8 D7-D0 Configuration Option RegisterBase + 00h in Attribute Memory Table CompactFlash Storage Card ConfigurationsTable Pin Replacement Changed Bit/Mask Bit Values Pin Replacement Register Base + 04h in Attribute MemoryI/O Transfer Function Socket and Copy Register Base + 06h in Attribute MemoryFunction Code True IDE Mode I/O Transfer FunctionTable Pcmcia Mode I/O Function Common Memory Transfer FunctionV1.1 CF-ATA Drive Register Set Definition and Protocol Table I/O Configurations Table Primary and Secondary I/O Decoding I/O Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode Addressing CF-ATA RegistersData Register Address 1F0h170hOffset 0,8,9 Table Data Register Access Error Register Address 1F1h171h Offset 1, 0Dh Read OnlyCylinder Low LBA 15-8 Register Address 1F4h174h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Sector Number LBA 7-0 Register Address 1F3h173h OffsetFigure Status & Alternate Status Register Device Control Register Address 3F6h376h Offset EhFigure Device Control Register Card Drive Address Register Address 3F7h377h Offset FhCF-ATA Command Description LBA CF-ATA Command SetDefinitions Cyl High Cyl Low Sec Num Sec Cnt Feature Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Bit CommandSec Num LBA Sec Cnt Erase Sectors C0hFormat Track 50h Drive Head LBA Cyl HighWord Default Total Data Field Type Information Identify Device EchBytes Total Data Field Type Information Word 6 Default Number of Sectors per Track Word 0 General ConfigurationWord 1 Default Number of Cylinders Word 3 Default Number of HeadsTotal Sectors Addressable in LBA Mode Word 49 Capabilities Bit 13 Standby TimerPIO Data Transfer Cycle Timing Mode Multiple Sector SettingRecommended Multiword DMA transfer cycle time Multiword DMA transferWord 64 Advanced PIO transfer modes supported Word 65 Minimum Multiword DMA transfer cycle timeWords 82-84 Features/command sets supported Words 85-87 Features/command sets enabledWord 68 Minimum PIO transfer cycle time with Iordy Word 91 Advanced power management level value Word 89 Time required for Security erase unit completionWord 128 Security Status Bit 8 Security Level Word 160 Power Requirement Description Value Maximum PIO mode timing selectedAdditional Requirements for CF Advanced Timing Modes Value Maximum Pcmcia IO timing mode Supported Value Maximum Multiword DMA timing mode supportedValue Current PIO timing mode selected Value Current Multiword DMA timing mode selectedInitialize Drive Parameters 91h Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureIdle 97h or E3h Idle Immediate 95h or E1hRead DMA C8h Read Buffer E4hRead Multiple C4h Read Verify Sectors 40h or 41h Read Sectors 20h or 21hRequest Sense 03h Recalibrate 1XhSeek 7Xh Table Extended Error CodesTable Feature Supported Set Features EFhSet Multiple Mode C6h Standby 96h or E2h Set Sleep Mode- 99h or E6hStandby Immediate 94h or E0h Translate Sector 87hTableTranslate Sector Information Wear Level F5h Write Buffer E8hWrite DMA CAh Write Multiple Command C5h Write Sectors 30h or 31h Write Multiple without Erase CDhWrite Verify 3Ch Write Sectors without Erase 38hBBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR 80X CompactFlash Card Error PostingCIS Description Address Data Description of Contents CIS functionAddress Data 5 4 Description of Contents CIS function Cistplconfig V1.1 MS IR IO RO a Address Data 5 4 3 2 1 Description of Contents CIS function Irqn LS AS NR RO a T
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