Transcend Information TS32M~1GCF80 dimensions V1.1

Page 9

TS32M~1GCF80

 

 

80X CompactFlash Card

 

 

 

 

 

 

 

 

 

 

 

 

D15 - D00

 

I/O

31,30,29,28,

These lines carry the Data, Commands and Status information between the host

(PC Card Memory Mode)

 

 

27,49,48,47,

and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB

 

 

 

 

6,5,4,3,2,

of the Odd Byte of the Word.

 

 

 

 

23, 22, 21

 

 

 

 

 

 

D15 - D00

 

 

 

This signal is the same as the PC Card Memory Mode signal.

(PC Card I/O Mode)

 

 

 

 

 

D15 - D00

 

 

 

In True IDE Mode, all Task File operations occur in byte mode on the low order

(True IDE Mode)

 

 

 

 

 

 

bus D[7:0] while all data transfers are 16 bit using D[15:0].

 

 

 

 

 

 

 

 

 

 

GND

 

--

1,50

Ground.

(PC Card Memory Mode)

 

 

 

 

 

GND

 

 

 

This signal is the same for all modes.

(PC Card I/O Mode)

 

 

 

 

 

GND

 

 

 

This signal is the same for all modes.

(True IDE Mode)

 

 

 

 

 

 

Signal Name

 

Dir.

Pin

Description

 

 

 

 

 

-INPACK

 

O

43

This signal is not used in this mode.

(PC Card Memory Mode)

 

 

 

 

 

-INPACK

 

 

 

The Input Acknowledge signal is asserted by the CompactFlash Storage Card

(PC Card I/O Mode)

 

 

 

when the card is selected and responding to an I/O read cycle at the address

Input Acknowledge

 

 

 

that is on the address bus. This signal is used by the host to control the enable of

 

 

 

 

 

 

 

 

 

 

any input data buffers between the CompactFlash Storage Card and the CPU.

DMARQ

 

 

 

This signal is a DMA Request that is used for DMA data transfers between host

 

 

 

 

 

(True IDE Mode)

 

 

 

and device. It shall be asserted by the device when it is ready to transfer data to

 

 

 

 

 

or from the host. For Multiword DMA transfers, the direction of data transfer is

 

 

 

 

 

controlled by -IORD and -IOWR. This signal is used in a handshake manner with

 

 

 

 

 

-DMACK, i.e., the device shall wait until the host asserts -DMACK before

 

 

 

 

 

negating DMARQ, and reasserting DMARQ if there is more data to transfer.

 

 

 

 

 

DMARQ shall not be driven when the device is not selected.

 

 

 

 

 

While a DMA operation is in progress, -CS0 and –CS1 shall be held negated

 

 

 

 

 

and the width of the transfers shall be 16 bits.

 

 

 

 

 

If there is no hardware support for DMA mode in the host, this output signal is not

 

 

 

 

 

used and should not be connected at the host. In this case, the BIOS must report

 

 

 

 

 

that DMA mode is not supported by the host so that device drivers will not

 

 

 

 

 

attempt DMA mode.

 

 

 

 

 

A host that does not support DMA mode and implements both PCMCIA and

 

 

 

 

 

True-IDE modes of operation need not alter the PCMCIA mode connections

 

 

 

 

 

while in True-IDE mode as long as this does not prevent proper operation in any

 

 

 

 

 

mode.

 

 

 

 

 

 

 

 

 

 

 

 

Transcend Information Inc.

 

9

 

 

 

 

 

 

V1.1

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Contents Dimensions Placement FeatureDescription 80X CompactFlash CardCHS and Capacity Ordering InformationCompactflash Card Specification Block Diagram Electrical Interface Pin Assignment and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode4V1.1 Signal Name Dir Pin Description Signal DescriptionCsel V1.1 Iord REG True IDE Mode As Iordy Input Leakage Current Electrical SpecificationParameter Symbol Min Max Unit Remark Input Characteristics CompactFlash interface I/O atMin Max Unit ParameterOutput Drive Type Output Drive Characteristics Signal Card Host Signal Interface150 μ a high state per socket TS32M~1GCF8080X CompactFlash CardAttribute Memory Read Timing Figure Attribute Memory Read Timing DiagramConfiguration Register Attribute Memory Write Timing Common Memory Read Timing Specification Cycle Time Mode 250 ns 120 ns 100 ns 80 nsMin Max Symbol Min Symbol Common Memory Write Timing Specification80X CompactFlash Card I/O Input Read Timing SpecificationCycle Time Mode 255 ns 120 ns 100 ns 80 ns 10 I/O Output Write Timing SpecificationMode True IDE PIO Mode Read/Write Timing SpecificationV1.1 True IDE Multiword DMA Mode Read/Write Timing Specification Multiple Function CompactFlash Storage Cards Card ConfigurationCE2 CE1 A10 A8-A4Function Mode Attribute Memory FunctionCE2 CE1 A10 D15-D8 D7-D0 Configuration Option RegisterBase + 00h in Attribute Memory Table CompactFlash Storage Card ConfigurationsTable Pin Replacement Changed Bit/Mask Bit Values Pin Replacement Register Base + 04h in Attribute MemoryI/O Transfer Function Socket and Copy Register Base + 06h in Attribute MemoryTable Pcmcia Mode I/O Function True IDE Mode I/O Transfer FunctionCommon Memory Transfer Function Function CodeV1.1 CF-ATA Drive Register Set Definition and Protocol Table I/O ConfigurationsTable Primary and Secondary I/O Decoding I/O Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode Addressing CF-ATA RegistersData Register Address 1F0h170hOffset 0,8,9 Table Data Register Access Error Register Address 1F1h171h Offset 1, 0Dh Read OnlySector Count Register Address 1F2h172h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetFigure Status & Alternate Status Register Device Control Register Address 3F6h376h Offset EhFigure Device Control Register Card Drive Address Register Address 3F7h377h Offset FhCF-ATA Command Description LBA CF-ATA Command SetDefinitions Execute Drive Diagnostic 90h Check Power Mode 98h or E5hBit Command Cyl High Cyl Low Sec Num Sec Cnt FeatureFormat Track 50h Erase Sectors C0hDrive Head LBA Cyl High Sec Num LBA Sec CntWord Default Total Data Field Type Information Identify Device EchBytes Total Data Field Type Information Word 1 Default Number of Cylinders Word 0 General ConfigurationWord 3 Default Number of Heads Word 6 Default Number of Sectors per TrackPIO Data Transfer Cycle Timing Mode Word 49 Capabilities Bit 13 Standby TimerMultiple Sector Setting Total Sectors Addressable in LBA ModeWord 64 Advanced PIO transfer modes supported Multiword DMA transferWord 65 Minimum Multiword DMA transfer cycle time Recommended Multiword DMA transfer cycle timeWords 82-84 Features/command sets supported Words 85-87 Features/command sets enabledWord 68 Minimum PIO transfer cycle time with Iordy Word 91 Advanced power management level value Word 89 Time required for Security erase unit completionWord 128 Security Status Bit 8 Security Level Word 160 Power Requirement Description Value Maximum PIO mode timing selectedAdditional Requirements for CF Advanced Timing Modes Value Current PIO timing mode selected Value Maximum Multiword DMA timing mode supportedValue Current Multiword DMA timing mode selected Value Maximum Pcmcia IO timing mode SupportedIdle 97h or E3h Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureIdle Immediate 95h or E1h Initialize Drive Parameters 91hRead DMA C8h Read Buffer E4hRead Multiple C4h Read Verify Sectors 40h or 41h Read Sectors 20h or 21hRequest Sense 03h Recalibrate 1XhSeek 7Xh Table Extended Error CodesTable Feature Supported Set Features EFhSet Multiple Mode C6h Standby 96h or E2h Set Sleep Mode- 99h or E6hStandby Immediate 94h or E0h Translate Sector 87hTableTranslate Sector Information Wear Level F5h Write Buffer E8hWrite DMA CAh Write Multiple Command C5h Write Sectors 30h or 31h Write Multiple without Erase CDhWrite Verify 3Ch Write Sectors without Erase 38hBBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR 80X CompactFlash Card Error PostingCIS Description Address Data Description of Contents CIS functionAddress Data 5 4 Description of Contents CIS function Cistplconfig V1.1 MS IR IO RO a Address Data 5 4 3 2 1 Description of Contents CIS function Irqn LS AS NR RO a T
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