Transcend Information TS32M~1GCF80 dimensions Device Control Register Address 3F6h376h Offset Eh

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TS32M~1GCF80

80X CompactFlash Card

 

 

 

It is Bit 27 in the Logical Block Address mode.

Bit 2 (HS2): when operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26 in the Logical Block Address mode.

Bit 1 (HS1): when operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode.

Bit 0 (HS0): when operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode.

5.5.9 Status & Alternate Status Registers (Address 1F7h[177h]&3F6h[376h]; Offsets 7 & Eh)

These registers return the CompactFlash Storage Card status when read by the host. Reading the Status register does clear a pending interrupt while reading the Auxiliary Status register does not. The status bits are described as follows:

Figure: Status & Alternate Status Register

Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1.

During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one.

Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to accept a command.

Bit 5 (DWF): This bit, if set, indicates a write fault has occurred.

Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready.

Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be transferred either to or from the host through the Data register.

During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one.

Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation.

Bit 1 (IDX): This bit is always set to 0.

Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. It is recommended that media access commands (such as Read Sectors and Write Sectors) that end with an error condition should have the address of the first sector in error in the command block registers.

5.5.10 Device Control Register (Address - 3F6h[376h]; Offset Eh)

This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows:

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Contents Description Placement FeatureDimensions 80X CompactFlash CardOrdering Information CHS and CapacityCompactflash Card Specification Block Diagram PC Card Memory Mode PC Card I/O Mode True IDE Mode4 Electrical Interface Pin Assignment and Pin TypeV1.1 Signal Description Signal Name Dir Pin DescriptionCsel V1.1 Iord REG True IDE Mode As Iordy Electrical Specification Input Leakage CurrentInput Characteristics CompactFlash interface I/O at Parameter Symbol Min Max Unit RemarkParameter Min Max UnitOutput Drive Type Output Drive Characteristics Signal Interface Signal Card HostTS32M~1GCF8080X CompactFlash Card 150 μ a high state per socketFigure Attribute Memory Read Timing Diagram Attribute Memory Read TimingConfiguration Register Attribute Memory Write Timing Common Memory Read Timing Specification Cycle Time Mode 250 ns 120 ns 100 ns 80 nsMin Max Symbol Common Memory Write Timing Specification Min SymbolI/O Input Read Timing Specification 80X CompactFlash Card10 I/O Output Write Timing Specification Cycle Time Mode 255 ns 120 ns 100 ns 80 nsTrue IDE PIO Mode Read/Write Timing Specification ModeV1.1 True IDE Multiword DMA Mode Read/Write Timing Specification CE2 CE1 Card ConfigurationMultiple Function CompactFlash Storage Cards A10 A8-A4Function Mode Attribute Memory FunctionCE2 CE1 A10 D15-D8 D7-D0 Table CompactFlash Storage Card Configurations Configuration Option RegisterBase + 00h in Attribute MemoryPin Replacement Register Base + 04h in Attribute Memory Table Pin Replacement Changed Bit/Mask Bit ValuesSocket and Copy Register Base + 06h in Attribute Memory I/O Transfer FunctionCommon Memory Transfer Function True IDE Mode I/O Transfer FunctionTable Pcmcia Mode I/O Function Function CodeV1.1 Table I/O Configurations CF-ATA Drive Register Set Definition and ProtocolI/O Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingMemory Mapped Addressing True IDE Mode Addressing CF-ATA RegistersData Register Address 1F0h170hOffset 0,8,9 Error Register Address 1F1h171h Offset 1, 0Dh Read Only Table Data Register AccessSector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetDevice Control Register Address 3F6h376h Offset Eh Figure Status & Alternate Status RegisterCard Drive Address Register Address 3F7h377h Offset Fh Figure Device Control RegisterCF-ATA Command Description CF-ATA Command Set LBADefinitions Bit Command Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Cyl High Cyl Low Sec Num Sec Cnt FeatureDrive Head LBA Cyl High Erase Sectors C0hFormat Track 50h Sec Num LBA Sec CntWord Default Total Data Field Type Information Identify Device EchBytes Total Data Field Type Information Word 3 Default Number of Heads Word 0 General ConfigurationWord 1 Default Number of Cylinders Word 6 Default Number of Sectors per TrackMultiple Sector Setting Word 49 Capabilities Bit 13 Standby TimerPIO Data Transfer Cycle Timing Mode Total Sectors Addressable in LBA ModeWord 65 Minimum Multiword DMA transfer cycle time Multiword DMA transferWord 64 Advanced PIO transfer modes supported Recommended Multiword DMA transfer cycle timeWords 82-84 Features/command sets supported Words 85-87 Features/command sets enabledWord 68 Minimum PIO transfer cycle time with Iordy Word 91 Advanced power management level value Word 89 Time required for Security erase unit completionWord 128 Security Status Bit 8 Security Level Word 160 Power Requirement Description Value Maximum PIO mode timing selectedAdditional Requirements for CF Advanced Timing Modes Value Current Multiword DMA timing mode selected Value Maximum Multiword DMA timing mode supportedValue Current PIO timing mode selected Value Maximum Pcmcia IO timing mode SupportedIdle Immediate 95h or E1h Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureIdle 97h or E3h Initialize Drive Parameters 91hRead Buffer E4h Read DMA C8hRead Multiple C4h Read Sectors 20h or 21h Read Verify Sectors 40h or 41hRecalibrate 1Xh Request Sense 03hTable Extended Error Codes Seek 7XhSet Features EFh Table Feature SupportedSet Multiple Mode C6h Set Sleep Mode- 99h or E6h Standby 96h or E2hStandby Immediate 94h or E0h Translate Sector 87hTableTranslate Sector Information Wear Level F5h Write Buffer E8hWrite DMA CAh Write Multiple Command C5h Write Multiple without Erase CDh Write Sectors 30h or 31hWrite Sectors without Erase 38h Write Verify 3Ch80X CompactFlash Card Error Posting BBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERRAddress Data Description of Contents CIS function CIS DescriptionAddress Data 5 4 Description of Contents CIS function Cistplconfig V1.1 MS IR IO RO a Address Data 5 4 3 2 1 Description of Contents CIS function Irqn LS AS NR RO a T
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