Transcend Information TS32M~1GCF80 dimensions Read Multiple C4h

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TS32M~1GCF80

80X CompactFlash Card

 

 

 

5.6.12 Read Multiple - C4h

Note: This specification requires that CompactFlash Cards support a multiple block count of 1 and permits larger values to be supported.

The Read Multiple command performs similarly to the Read Sectors command. Interrupts are not generated on every sector, but on the transfer of a block, which contains the number of sectors defined by a Set Multiple command.

Command execution is identical to the Read Sectors operation except that the number of sectors defined by a Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector.

The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which shall be executed prior to the Read Multiple command. When the Read Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where

n = (sector count) modulo (block count).

If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read Multiple commands are disabled, the Read Multiple operation is rejected with an Aborted Command error. Disk errors encountered during Read Multiple commands are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer shall take place as it normally would, including transfer of corrupted data, if any.

Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same as that on a Read Sector(s) Command. This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register.

At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector read.

If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer.

Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block that contained the error.

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Contents Placement Feature DimensionsDescription 80X CompactFlash CardOrdering Information CHS and CapacityCompactflash Card Specification Block Diagram PC Card Memory Mode PC Card I/O Mode True IDE Mode4 Electrical Interface Pin Assignment and Pin TypeV1.1 Signal Description Signal Name Dir Pin DescriptionCsel V1.1 Iord REG True IDE Mode As Iordy Electrical Specification Input Leakage CurrentInput Characteristics CompactFlash interface I/O at Parameter Symbol Min Max Unit RemarkParameter Min Max UnitOutput Drive Type Output Drive Characteristics Signal Interface Signal Card HostTS32M~1GCF8080X CompactFlash Card 150 μ a high state per socketFigure Attribute Memory Read Timing Diagram Attribute Memory Read TimingConfiguration Register Attribute Memory Write Timing Common Memory Read Timing Specification Cycle Time Mode 250 ns 120 ns 100 ns 80 nsMin Max Symbol Common Memory Write Timing Specification Min SymbolI/O Input Read Timing Specification 80X CompactFlash Card10 I/O Output Write Timing Specification Cycle Time Mode 255 ns 120 ns 100 ns 80 nsTrue IDE PIO Mode Read/Write Timing Specification ModeV1.1 True IDE Multiword DMA Mode Read/Write Timing Specification Card Configuration Multiple Function CompactFlash Storage CardsCE2 CE1 A10 A8-A4Function Mode Attribute Memory FunctionCE2 CE1 A10 D15-D8 D7-D0 Table CompactFlash Storage Card Configurations Configuration Option RegisterBase + 00h in Attribute MemoryPin Replacement Register Base + 04h in Attribute Memory Table Pin Replacement Changed Bit/Mask Bit ValuesSocket and Copy Register Base + 06h in Attribute Memory I/O Transfer FunctionTrue IDE Mode I/O Transfer Function Table Pcmcia Mode I/O FunctionCommon Memory Transfer Function Function CodeV1.1 Table I/O Configurations CF-ATA Drive Register Set Definition and ProtocolI/O Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingMemory Mapped Addressing True IDE Mode Addressing CF-ATA RegistersData Register Address 1F0h170hOffset 0,8,9 Error Register Address 1F1h171h Offset 1, 0Dh Read Only Table Data Register AccessFeature Register Address 1F1h171h Offset 1, 0Dh Write Only Sector Count Register Address 1F2h172h OffsetSector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetDevice Control Register Address 3F6h376h Offset Eh Figure Status & Alternate Status RegisterCard Drive Address Register Address 3F7h377h Offset Fh Figure Device Control RegisterCF-ATA Command Description CF-ATA Command Set LBADefinitions Check Power Mode 98h or E5h Execute Drive Diagnostic 90hBit Command Cyl High Cyl Low Sec Num Sec Cnt FeatureErase Sectors C0h Format Track 50hDrive Head LBA Cyl High Sec Num LBA Sec CntWord Default Total Data Field Type Information Identify Device EchBytes Total Data Field Type Information Word 0 General Configuration Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 6 Default Number of Sectors per TrackWord 49 Capabilities Bit 13 Standby Timer PIO Data Transfer Cycle Timing ModeMultiple Sector Setting Total Sectors Addressable in LBA ModeMultiword DMA transfer Word 64 Advanced PIO transfer modes supportedWord 65 Minimum Multiword DMA transfer cycle time Recommended Multiword DMA transfer cycle timeWords 82-84 Features/command sets supported Words 85-87 Features/command sets enabledWord 68 Minimum PIO transfer cycle time with Iordy Word 91 Advanced power management level value Word 89 Time required for Security erase unit completionWord 128 Security Status Bit 8 Security Level Word 160 Power Requirement Description Value Maximum PIO mode timing selectedAdditional Requirements for CF Advanced Timing Modes Value Maximum Multiword DMA timing mode supported Value Current PIO timing mode selected Value Current Multiword DMA timing mode selected Value Maximum Pcmcia IO timing mode SupportedDrive Cyl High Cyl Low Sec Num Sec Cnt Feature Idle 97h or E3hIdle Immediate 95h or E1h Initialize Drive Parameters 91hRead Buffer E4h Read DMA C8hRead Multiple C4h Read Sectors 20h or 21h Read Verify Sectors 40h or 41hRecalibrate 1Xh Request Sense 03hTable Extended Error Codes Seek 7XhSet Features EFh Table Feature SupportedSet Multiple Mode C6h Set Sleep Mode- 99h or E6h Standby 96h or E2hStandby Immediate 94h or E0h Translate Sector 87hTableTranslate Sector Information Wear Level F5h Write Buffer E8hWrite DMA CAh Write Multiple Command C5h Write Multiple without Erase CDh Write Sectors 30h or 31hWrite Sectors without Erase 38h Write Verify 3Ch80X CompactFlash Card Error Posting BBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERRAddress Data Description of Contents CIS function CIS DescriptionAddress Data 5 4 Description of Contents CIS function Cistplconfig V1.1 MS IR IO RO a Address Data 5 4 3 2 1 Description of Contents CIS function Irqn LS AS NR RO a T
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