Texas Instruments TMS320C6457 DSP Stopping Test Unit, SNR Threshold Termination, CRC Termination

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Standalone (SA) Mode

The CRC-based stopping criterion can be used by setting the CRC polynomial length (CRCLEN) and the number of CRC iterations required to pass CRCITERPASS. After each iteration, hard decisions are computed and a CRC is performed. The CRC polynomial is a programmable 32-bit number. To avoid situations where a CRC test passes for a very noisy frame of data, the hard decisions need to pass the CRC test for a number of consecutive iterations, which is user-defined via the CRCITERPASS bit field.

4.4Stopping Test Unit

Turbo decoders are iterative decoders. Each iteration consists of two MAP decodes except the last iteration that executes only the first MAP decode. The turbo decoder can iterate up to 32 iterations. The decoder will continue to iterate until one of the following conditions occur: meet parameter conditions, CRC passed, or SNR threshold passed.

4.4.1SNR Threshold Termination

The stopping criteria algorithm generates the first two moments of the extrinsics, generates an SNR ratio, and compares the ratio with a threshold. If the calculated ratio exceeds the threshold, then the decoder has found an optimum solution. The decoder can then stop executing any further iterations. The calculated SNR ratio is generated after each MAP process. The threshold is a user input and can range from 0 to 100. Larger thresholds give better results but require more iterations. Smaller thresholds require fewer iterations and give can give poorer results. Setting the threshold to 0 disables the stopping criteria algorithm.

The stopping criteria contains two parts. The first part executes on each extrinsic value. The sum of the extrinsics and the sum of the extrinsics squared are calculated. The second part is executed once at the end of each MAP block. The first moment is squared and multiplied by the sum of 1 plus the inverse of the threshold. The second moment is multiplied by the number of symbols per frame. The two results are compared. If the result is positive, then the stopping criteria has been met.

The turbo decoder will generate a block of extrinsics after each MAP decode. The SNR stopping criteria block calculates the mean and the variance for this block. It will divide the two and compare the result with the snr_threshold. If the result is greater then the snr_threshold for two consecutive MAP decodes, then the decoder will stop executing. The DSP sets the snr_threshold parameter. The SNR stopping criteria can be turned off with a value of 0. Enabled values for snr_threshold range from 1 to 100. A value of 100 gives the best BER performance at a cost of the most iterations executed, and a value of 1 gives the worst BER performance at a cost of the fewest iterations. Recommended setting for this parameter is 100.

4.4.2CRC Termination

A frame of data is sent through a CRC block which appends crc_length number of bits to the frame. This frame is encoded by the turbo encoder. The polynomial for the CRC check is defined with the crc_poly parameter. The turbo decoder will generate hard decision bits after each non-interleaved MAP decode. These bits are processed by the CRC block within the decoder. If the last crc_length bits match the CRC pattern, then the CRC check has passed. The turbo decoder will stop executing after CRCITERPASS number of consecutive CRC passes as programmed in TCPIC4.

The coefficients and the size of the CRC polynomial are programmable. The size of the polynomial is defined with the parameter crc_length and can be set from 0 to 32 bits. A value of 0 disables the CRC check, values between 1 and 32 enable the CRC check. The CRC polynomial is defined with the crc_poly parameter. The CRC unit will not be enabled until the decoder iteration count is equal or greater than the min_iter parameter. The turbo decoder will generate hard decisions after each non-interleaved MAP decode. These bits are processed by the CRC block within the decoder. If the last set of frame bits match the CRC pattern, then the CRC check has passed. The turbo decoder must pass a number of consecutive iterations to terminate before max_iter. The number of consecutive iterations passed is defined with the crc_iter_pass parameter. The crc_iter_pass parameter can be set from 0 to 31, a zero is equal to 1 iteration. The dec_pass output parameter will be set to a 1 if the decoder terminated due to a passing CRC.

During the sub-block execution, up to 256 sets of data will be stored in a double buffered RAM whose size is 265x7x2. Two bits each will be stored for x0, p0, and p1. One bit is the sign bit and the other bit is set if the symbol is equal to a zero. These 6 bits will be used for re-encoding. The seventh bit will be the hard decision bit. This bit is the sign of the following summation: (x+a+w).

SPRUGK1–March 2009

TMS320C6457 Turbo-Decoder Coprocessor 2

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments TrademarksTMS320C6457 Turbo-Decoder Coprocessor FeaturesIntroduction GPP and IS2000 Turbo-Encoder Block DiagramOverview GPP and IS2000 Turbo-Decoder Block DiagramTCP2 Mode Standalone SA ModeSystematic and Parity Data Input Data FormatSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Stopping Criteria Output Decision Data FormatInterleaver Indexes Interleaver DataCRC Termination Stopping Test UnitSNR Threshold Termination Parameter Termination Shared-Processing SP ModeMaximum Iterations Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Rsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 Output Data FormatPriori Data TCP2 Registers RegistersTCP2 RAMs NameRegisters Peripheral Identification Register PID Field Descriptions Peripheral Identification Register PIDBit Field DescriptionBit Field Value Description TCP2 Input Configuration Register 0 TCPIC0TCP2 Input Configuration Register 2 TCPIC2 TCP2 Input Configuration Register 1 TCPIC1SNR MaxitTCP2 Input Configuration Register 3 TCPIC3 Crclen TCP2 Input Configuration Register 4 TCPIC4Crciterpass Tail Symbols TCP2 Input Configuration Register 5 TCPIC5CRC Examples CrcpolyTAIL1 TCP2 Input Configuration Register 6 TCPIC6TAIL2 10 TCP2 Input Configuration Register 7 TCPIC7TAIL3 11 TCP2 Input Configuration Register 8 TCPIC8TAIL4 12 TCP2 Input Configuration Register 9 TCPIC9TAIL5 13 TCP2 Input Configuration Register 10 TCPIC1014 TCP2 Input Configuration Register 11 TCPIC11 TCP2 Input Configuration Register 11 TCPIC11 16 TCP2 Input Configuration Register 13 TCPIC13 15 TCP2 Input Configuration Register 12 TCPIC12EXTSCALE03 EXTSCALE47EXTSCALE811 17 TCP2 Input Configuration Register 14 TCPIC14Extrinsic Scale Registers 18 TCP2 Input Configuration Register 15 TCPIC15EXTSCALE1215 Iteration Number20 TCP2 Output Parameter Register 1 TCPOUT1 19 TCP2 Output Parameter Register 0 TCPOUT0TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions22 TCP2 Execution Register Tcpexe 21 TCP2 Output Parameter Register 2 TCPOUT2TCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions TCP2 Execution Register Tcpexe Field DescriptionsTCP2 Endian Register Tcpend Field Descriptions 23 TCP2 Endian Register TcpendEndian Extr Intr EndianextrTCP2 Error Register Tcperr Field Descriptions 24 TCP2 Error Register TcperrSubframe length Tcpstate 25 TCP2 Status Register TcpstatTCP2 Status Register Tcpstat Field Descriptions Waiting for RAM extrinsic memory 0 to be read TCP2 Emulation Register Tcpemu Field Descriptions 26 TCP2 Emulation Register TcpemuSoft = Soft FreeData Memory for Systematic Endianness6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 Data MemoryEN = 0 Big-Endian Mode Rate = 1/4 Hard Decision Data EN = 0 Big-Endian Mode Rate = 3/4Tcpendian Register for Endianness Manager Hard Decisions in DSP MemoryData HD1 HD0Endianintr = Tcpendian Programming RegisterInterleaver Indexes in DSP Memory Data Native Format DSP Memory FormatINTER3 INTER2 INTER1 INTER0 INTER0 INTER1 INTER2 INTER3Extrinsic in DSP Memory Endianextr = Extrinsic DataEndianextr = Data Source Kernel Endianextr = EXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 ArchitectureEXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 Sub-block and Sliding Window Segmentation MAP Unit Block DiagramExamples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Subframe Segmentation SP mode onlyReliability and Prolog Length Calculation Code Rates Added FeaturesProgramming Valid Re-Encode Symbols Used for ComparisonInput Sign Log EquationEDMA3 Parameters in Shared Processing SP Mode EDMA3 Parameters in Standalone SA ModeEDMA3 Resources 1 TCP2 Dedicated EDMA3 ResourcesInput Configuration Parameters Transfer Programming Standalone SA ModeEDMA3 Programming Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Output Parameters Transfer Input Configurations Parameters ProgrammingOpmod TCPIC0 Programming Shared-Processing SP ModeInter TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Inter TCPIC0 Inter = Outf Output ParametersEvents Generation Errors and Status Debug Mode Pause After Each MapErrors Error Status ERRUnexpected Memory Access ACC Unexpected Signal to Noise Ratio SNRUnexpected Frame Length F Unexpected Prolog Length PStatus 13.2.13 TCP2 Active Iteration Status Activeiter 13.2.12 TCP2 Active State Status Activestate13.2.14 TCP2 SNR Status snrexceed 13.2.15 TCP2 CRC Status CrcpassRfid Products ApplicationsDSP
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