Texas Instruments TMS320C6457 DSP manual Programming Standalone SA Mode, EDMA3 Programming

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Programming

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9.2Programming Standalone (SA) Mode

Table 42 highlights the required EDMA3 resources to perform a standalone (SA) mode decoding. Each set of EDMA3 parameters uses the EDMA3 linking capabilities. Section 9.2.1 details the EDMA3 transfers programming and Section 9.2.2 details the input parameters programming. Any notification mechanism to flag that a user-channel has just been decoded is left to you. Suggested implementation is to use the EDMA3 interrupt generation capabilities [see the TMS320C6457 DSP Enhanced Direct Memory Access (EDMA3) Controller Reference Guide (SPRUGK6)] and program the EDMA3 to generate an interrupt after the user-channel's last TCPREVT synchronized EDMA3 transfer has completed.

9.2.1EDMA3 Programming

9.2.1.1Input Configuration Parameters Transfer

This EDMA3 transfer to the input configuration parameters is a 16-word TCPXEVT frame synchronized transfer. The parameters should be set as:

∙OPTIONS

–ITCCEN = 0 (Intermediate transfer complete chaining is disabled)

–TCCEN = 0 (Transfer complete chaining is disabled)

–ITCINTEN = 0 (Intermediate transfer complete interrupt is disabled)

–TCINTEN = 0 (Transfer complete interrupt is disabled)

–TCC = 1 to 63 (Transfer Complete Code)

–TCCMODE = 0 (Normal Completion)

–FWID = Don't care

–STAT = 0 (Entry is updated as normal)

–SYNCDIM = 0 (A-Sync. Each event triggers the transfer of ACNT elements.)

–DAM = 0 (Dst addressing within an array increments. Dst is not a FIFO.)

–SAM = 0 (Src addressing within an array increments. Source is not a FIFO.)

∙SOURCE ADDRESS: User input configuration parameters start address (must be double-word aligned)

∙ACNT = 64 (No of bytes in an array - 16 32 bit Input Configurations to be transferred)

∙BCNT = 1 (No of arrays of length ACNT)

∙DESTINATION ADDRESS: TCPIC0 (5000 0000h)

∙SRCBIDX = 0 (Source 2nd Dimension Index)

∙DSTBIDX = 0 (Destination 2nd Dimension Index)

∙SRCCIDX = 0 (Source 3rd Dimension Index)

∙DSTCIDX = 0 (Destination 3rd Dimension Index)

∙CCNT = 1 (No of frames in a block)

∙BCNTRLD: Don't care

∙LINK ADDRESS: Address in the EDMA3 PaRAM of the EDMA3 parameters associated with the systematics and parities

Upon completion, this EDMA3 transfer is linked to the EDMA3 for systematics and parities transfer parameters.

9.2.1.2Systematics and Parities Transfer

This EDMA3 transfer to the systematics and parities memory is a TCPXEVT frame-synchronized transfer. The parameters should be set as:

∙OPTIONS:

–ITCCEN = 0 (Intermediate transfer complete chaining is disabled)

–TCCEN = 0 (Transfer complete chaining is disabled)

–ITCINTEN = 0 (Intermediate transfer complete interrupt is disabled)

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TMS320C6457 Turbo-Decoder Coprocessor 2

SPRUGK1–March 2009

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Related Documentation From Texas Instruments About This ManualNotational Conventions TrademarksFeatures TMS320C6457 Turbo-Decoder CoprocessorGPP and IS2000 Turbo-Encoder Block Diagram IntroductionGPP and IS2000 Turbo-Decoder Block Diagram OverviewStandalone SA Mode TCP2 ModeInput Data Format Systematic and Parity DataSP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Interleaver Indexes Output Decision Data FormatStopping Criteria Interleaver DataStopping Test Unit SNR Threshold TerminationCRC Termination Maximum Iterations Shared-Processing SP ModeParameter Termination Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Output Data Format Priori DataRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 TCP2 RAMs RegistersTCP2 Registers NameRegisters Bit Field Peripheral Identification Register PIDPeripheral Identification Register PID Field Descriptions DescriptionTCP2 Input Configuration Register 0 TCPIC0 Bit Field Value DescriptionSNR TCP2 Input Configuration Register 1 TCPIC1TCP2 Input Configuration Register 2 TCPIC2 MaxitTCP2 Input Configuration Register 3 TCPIC3 TCP2 Input Configuration Register 4 TCPIC4 CrciterpassCrclen CRC Examples TCP2 Input Configuration Register 5 TCPIC5Tail Symbols CrcpolyTCP2 Input Configuration Register 6 TCPIC6 TAIL110 TCP2 Input Configuration Register 7 TCPIC7 TAIL211 TCP2 Input Configuration Register 8 TCPIC8 TAIL312 TCP2 Input Configuration Register 9 TCPIC9 TAIL413 TCP2 Input Configuration Register 10 TCPIC10 14 TCP2 Input Configuration Register 11 TCPIC11TAIL5 TCP2 Input Configuration Register 11 TCPIC11 EXTSCALE03 15 TCP2 Input Configuration Register 12 TCPIC1216 TCP2 Input Configuration Register 13 TCPIC13 EXTSCALE4717 TCP2 Input Configuration Register 14 TCPIC14 EXTSCALE811EXTSCALE1215 18 TCP2 Input Configuration Register 15 TCPIC15Extrinsic Scale Registers Iteration NumberTCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions 19 TCP2 Output Parameter Register 0 TCPOUT020 TCP2 Output Parameter Register 1 TCPOUT1 TCP2 Output Parameter Register 1 TCPOUT1 Field DescriptionsTCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions 21 TCP2 Output Parameter Register 2 TCPOUT222 TCP2 Execution Register Tcpexe TCP2 Execution Register Tcpexe Field DescriptionsEndian Extr Intr 23 TCP2 Endian Register TcpendTCP2 Endian Register Tcpend Field Descriptions Endianextr24 TCP2 Error Register Tcperr TCP2 Error Register Tcperr Field DescriptionsSubframe length 25 TCP2 Status Register Tcpstat TCP2 Status Register Tcpstat Field DescriptionsTcpstate Waiting for RAM extrinsic memory 0 to be read Soft = 26 TCP2 Emulation Register TcpemuTCP2 Emulation Register Tcpemu Field Descriptions Soft FreeEndianness Data Memory for SystematicData Memory 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116EN = 0 Big-Endian Mode Rate = 1/4 EN = 0 Big-Endian Mode Rate = 3/4 Hard Decision DataData Hard Decisions in DSP MemoryTcpendian Register for Endianness Manager HD1 HD0Interleaver Indexes in DSP Memory Tcpendian Programming RegisterEndianintr = Data Native Format DSP Memory FormatINTER0 INTER1 INTER2 INTER3 INTER3 INTER2 INTER1 INTER0Extrinsic Data Endianextr =Extrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = Architecture EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0EXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 MAP Unit Block Diagram Sub-block and Sliding Window SegmentationSubframe Segmentation SP mode only Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and WinrelReliability and Prolog Length Calculation Added Features Code RatesInput Sign Valid Re-Encode Symbols Used for ComparisonProgramming Log EquationEDMA3 Resources EDMA3 Parameters in Standalone SA ModeEDMA3 Parameters in Shared Processing SP Mode 1 TCP2 Dedicated EDMA3 ResourcesEDMA3 Programming Programming Standalone SA ModeInput Configuration Parameters Transfer Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Input Configurations Parameters Programming Output Parameters TransferInter TCPIC0 Programming Shared-Processing SP ModeOpmod TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Output Parameters Events GenerationInter TCPIC0 Inter = Outf Errors Debug Mode Pause After Each MapErrors and Status Error Status ERRUnexpected Frame Length F Unexpected Signal to Noise Ratio SNRUnexpected Memory Access ACC Unexpected Prolog Length PStatus 13.2.14 TCP2 SNR Status snrexceed 13.2.12 TCP2 Active State Status Activestate13.2.13 TCP2 Active Iteration Status Activeiter 13.2.15 TCP2 CRC Status CrcpassProducts Applications DSPRfid
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