Texas Instruments TMS320C6457 DSP manual TCP2 Shared Processing Block Diagram

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Shared-Processing (SP) Mode

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Figure 19. TCP2 Shared Processing Block Diagram

MAP 1: Parity A or

MAP 2: Parity A'

MAP 1: Parity B or

MAP 2: Parity B'

Void input

MAP 1: Systemic or

MAP 2: Interleaved (systematic)

MAP 1: De−interlaced (Apriori 2) or MAP 2: Interleaved (Apriori 1)

MAP decoder unit

MAP 1: Apriori 1 or	Extrinsic saved as apriori
MAP 2: Apriori 2

5.1Input Data Format

5.1.1Systematic and Parity Data

The original systematic and parity data is organized as described in Section 4.1.1. The DSP has to split the data for MAP0 and MAP1 as shown in the following figures. The base address must be double-word aligned. Interleaved systematic data (X.) must be calculated by the DSP given the interleaver table (see Section 4.1.2). For big-endian configuration, see Section 7.

Figure 20. Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and 3/4

63:62	61:56	55:50	49:44	43:38	37:32	31:30	29:24	23:18	17:12	11:6	5:0
RSVD	SP9	SP8	SP7	SP6	SP5	RSVD	SP4	SP3	SP2	SP1	SP0

Figure 21. EN = 1 (Little-Endian Mode) Rate = 1/2

		Word					Word
		N + 1					N
SP9	SP8	SP7	SP6	SP5	SP4	SP3	SP3	SP3	SP0
0	A1'	0	0	X1	0	0	0	0	X0
		Word					Word
		N + 3					N + 2
SP9	SP8	SP7	SP6	SP5	SP4	SP3	SP3	SP3	SP0
0	A3'	0	0	X3	0	0	0	0	X2

Figure 22. EN = 0 (Big-Endian Mode) Rate = 1/2

			Word					Word
			N					N + 1
	SP4	SP3	SP2	SP1	SP0	SP9	SP8	SP7	SP6	SP5
	0	0	0	A0	X0	0	A1'	0	0	X1
			Word					Word
			N + 2					N + 3
	SP4	SP3	SP2	SP1	SP0	SP9	SP8	SP7	SP6	SP5
	0	0	0	A2	X2	0	A3'	0	0	X3
22	TMS320C6457 Turbo-Decoder Coprocessor 2								SPRUGK1–March 2009

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Related Documentation From Texas Instruments About This ManualNotational Conventions TrademarksFeatures TMS320C6457 Turbo-Decoder CoprocessorGPP and IS2000 Turbo-Encoder Block Diagram IntroductionGPP and IS2000 Turbo-Decoder Block Diagram OverviewStandalone SA Mode TCP2 ModeInput Data Format Systematic and Parity DataSP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Interleaver Indexes Output Decision Data FormatStopping Criteria Interleaver DataSNR Threshold Termination Stopping Test UnitCRC Termination Maximum Iterations Shared-Processing SP ModeParameter Termination Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Priori Data Output Data FormatRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 TCP2 RAMs RegistersTCP2 Registers NameRegisters Bit Field Peripheral Identification Register PIDPeripheral Identification Register PID Field Descriptions DescriptionTCP2 Input Configuration Register 0 TCPIC0 Bit Field Value DescriptionSNR TCP2 Input Configuration Register 1 TCPIC1TCP2 Input Configuration Register 2 TCPIC2 MaxitTCP2 Input Configuration Register 3 TCPIC3 Crciterpass TCP2 Input Configuration Register 4 TCPIC4Crclen CRC Examples TCP2 Input Configuration Register 5 TCPIC5Tail Symbols CrcpolyTCP2 Input Configuration Register 6 TCPIC6 TAIL110 TCP2 Input Configuration Register 7 TCPIC7 TAIL211 TCP2 Input Configuration Register 8 TCPIC8 TAIL312 TCP2 Input Configuration Register 9 TCPIC9 TAIL414 TCP2 Input Configuration Register 11 TCPIC11 13 TCP2 Input Configuration Register 10 TCPIC10TAIL5 TCP2 Input Configuration Register 11 TCPIC11 EXTSCALE03 15 TCP2 Input Configuration Register 12 TCPIC1216 TCP2 Input Configuration Register 13 TCPIC13 EXTSCALE4717 TCP2 Input Configuration Register 14 TCPIC14 EXTSCALE811EXTSCALE1215 18 TCP2 Input Configuration Register 15 TCPIC15Extrinsic Scale Registers Iteration NumberTCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions 19 TCP2 Output Parameter Register 0 TCPOUT020 TCP2 Output Parameter Register 1 TCPOUT1 TCP2 Output Parameter Register 1 TCPOUT1 Field DescriptionsTCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions 21 TCP2 Output Parameter Register 2 TCPOUT222 TCP2 Execution Register Tcpexe TCP2 Execution Register Tcpexe Field DescriptionsEndian Extr Intr 23 TCP2 Endian Register TcpendTCP2 Endian Register Tcpend Field Descriptions Endianextr24 TCP2 Error Register Tcperr TCP2 Error Register Tcperr Field DescriptionsSubframe length TCP2 Status Register Tcpstat Field Descriptions 25 TCP2 Status Register TcpstatTcpstate Waiting for RAM extrinsic memory 0 to be read Soft = 26 TCP2 Emulation Register TcpemuTCP2 Emulation Register Tcpemu Field Descriptions Soft FreeEndianness Data Memory for SystematicData Memory 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116EN = 0 Big-Endian Mode Rate = 1/4 EN = 0 Big-Endian Mode Rate = 3/4 Hard Decision DataData Hard Decisions in DSP MemoryTcpendian Register for Endianness Manager HD1 HD0Interleaver Indexes in DSP Memory Tcpendian Programming RegisterEndianintr = Data Native Format DSP Memory FormatINTER0 INTER1 INTER2 INTER3 INTER3 INTER2 INTER1 INTER0Endianextr = Extrinsic DataExtrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 ArchitectureEXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 MAP Unit Block Diagram Sub-block and Sliding Window SegmentationSubframe Segmentation SP mode only Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and WinrelReliability and Prolog Length Calculation Added Features Code RatesInput Sign Valid Re-Encode Symbols Used for ComparisonProgramming Log EquationEDMA3 Resources EDMA3 Parameters in Standalone SA ModeEDMA3 Parameters in Shared Processing SP Mode 1 TCP2 Dedicated EDMA3 ResourcesEDMA3 Programming Programming Standalone SA ModeInput Configuration Parameters Transfer Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Input Configurations Parameters Programming Output Parameters TransferInter TCPIC0 Programming Shared-Processing SP ModeOpmod TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Events Generation Output ParametersInter TCPIC0 Inter = Outf Errors Debug Mode Pause After Each MapErrors and Status Error Status ERRUnexpected Frame Length F Unexpected Signal to Noise Ratio SNRUnexpected Memory Access ACC Unexpected Prolog Length PStatus 13.2.14 TCP2 SNR Status snrexceed 13.2.12 TCP2 Active State Status Activestate13.2.13 TCP2 Active Iteration Status Activeiter 13.2.15 TCP2 CRC Status CrcpassDSP Products ApplicationsRfid