Texas Instruments TMS320C6457 DSP manual Programming Shared-Processing SP Mode, Opmod TCPIC0

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Programming

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The minimum number of iterations (MINIT bits in TCPIC3) should be selected as a function of the overall system performance (minimum iterations 1 to 31) when SNR stopping criteria is used.

The INPUTSIGN bit can be enabled or disabled in TCPIC3 (0 = Use channel input data as is, 1 = multiply channel input data by -1).

The OUTORDER bit can be enabled or disabled in TCPIC3 (0 = output bit ordering from 0 to 31, 1 = output bit ordering from 31 to 0).

The EPRORED bit can be enabled or disabled in TCPIC3 (0 = prolog reduction disabled, 1 = prolog reduction enabled).

The CRC length and CRC iterations (TCPIC4) and CRC Polyn bits (TCPIC5) should be selected as a function of the overall system performance. A value 0 disables the CRC stopping criteria algorithm.

The TAIL1, TAIL2, TAIL3, TAIL4, TAIL5, and TAIL6 bits should be programmed as described in Section 6.8 through Section 6.13, respectively.

The Extrinsic Scaling factors can be selected in registers TCPIC12, TCPIC13, TCPIC14, and TCPIC15.

Table 44. Input Configuration Parameters Settings in Standalone (SA) Mode

Bit Field

Register

Value

OPMOD

TCPIC0

OPMOD = 00: SA Mode

INTER

TCPIC0

INTER = 0 if no new interleaver table is needed; otherwise, INTER = 1

OUTF

TCPIC0

OUTF = 1 if TCPREVT is to be generated for the output parameters load;

 

 

otherwise, OUTF = 0

9.3Programming Shared-Processing (SP) Mode

In shared mode, the DSP must do more work and work closely with the TCP2. The DSP breaks the large frame into smaller frames of 20,480 or less. Each one of these frames is called a subframe. The size of all the subframes (except the last subframe) must be divisible by 256. Note that the frame_length listed in the shared-processing mode is the length of the subframes and not the length of the frame. The TCP will treat each subframe as its own frame of data.

To decode the whole frame, follow these steps:

1.DSP sends subframe systematic, parity and extrinsic data to TCP2.

2.TCP2 executes two MAP decoders for each iteration.

3.DSP reads the intermediate results (extrinsics).

4.DSP interleaves or de-interleaves data.

5.Steps 1 to 4 are repeated for all subframes.

The opmod parameter defines which subframe the TCP2 is decoding. Opmode is set to 1 for the first subframe, opmode is set to 2 for the middle subframe(s), and opmode is set to 3 for the last subframe.

Table 43 highlights the required EDMA3 resources to perform a shared-processing (SP) mode decoding. As in standalone (SA) mode decoding, each set of EDMA3 parameters uses the EDMA3 linking capabilities. In addition, the a priori data transfer is done using the EDMA3 alternate transfer chaining capabilities. Section 9.3.1 details the EDMA3 transfers programming and Section 9.3.2 details the input parameters programming. It should be noted that any stopping criteria algorithm has to be implemented by the CPU.

Any notification mechanism to flag that a user-channel has just been decoded is left to you. Suggested implementation is to use the EDMA3 interrupt generation capabilities [see TMS320C6457 DSP Enhanced Direct Memory Access (EDMA3) Controller Reference Guide (SPRUGK6)] and program the EDMA3 to generate an interrupt after the user-channel's last TCPREVT synchronized EDMA3 transfer has completed.

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TMS320C6457 Turbo-Decoder Coprocessor 2

SPRUGK1–March 2009

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Related Documentation From Texas Instruments About This ManualNotational Conventions TrademarksFeatures TMS320C6457 Turbo-Decoder CoprocessorGPP and IS2000 Turbo-Encoder Block Diagram IntroductionGPP and IS2000 Turbo-Decoder Block Diagram OverviewStandalone SA Mode TCP2 ModeInput Data Format Systematic and Parity DataSP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Interleaver Indexes Output Decision Data FormatStopping Criteria Interleaver DataSNR Threshold Termination Stopping Test UnitCRC Termination Maximum Iterations Shared-Processing SP ModeParameter Termination Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Priori Data Output Data FormatRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 TCP2 RAMs RegistersTCP2 Registers NameRegisters Bit Field Peripheral Identification Register PIDPeripheral Identification Register PID Field Descriptions DescriptionTCP2 Input Configuration Register 0 TCPIC0 Bit Field Value DescriptionSNR TCP2 Input Configuration Register 1 TCPIC1TCP2 Input Configuration Register 2 TCPIC2 MaxitTCP2 Input Configuration Register 3 TCPIC3 Crciterpass TCP2 Input Configuration Register 4 TCPIC4Crclen CRC Examples TCP2 Input Configuration Register 5 TCPIC5Tail Symbols CrcpolyTCP2 Input Configuration Register 6 TCPIC6 TAIL110 TCP2 Input Configuration Register 7 TCPIC7 TAIL211 TCP2 Input Configuration Register 8 TCPIC8 TAIL312 TCP2 Input Configuration Register 9 TCPIC9 TAIL414 TCP2 Input Configuration Register 11 TCPIC11 13 TCP2 Input Configuration Register 10 TCPIC10TAIL5 TCP2 Input Configuration Register 11 TCPIC11 EXTSCALE03 15 TCP2 Input Configuration Register 12 TCPIC1216 TCP2 Input Configuration Register 13 TCPIC13 EXTSCALE4717 TCP2 Input Configuration Register 14 TCPIC14 EXTSCALE811EXTSCALE1215 18 TCP2 Input Configuration Register 15 TCPIC15Extrinsic Scale Registers Iteration NumberTCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions 19 TCP2 Output Parameter Register 0 TCPOUT020 TCP2 Output Parameter Register 1 TCPOUT1 TCP2 Output Parameter Register 1 TCPOUT1 Field DescriptionsTCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions 21 TCP2 Output Parameter Register 2 TCPOUT222 TCP2 Execution Register Tcpexe TCP2 Execution Register Tcpexe Field DescriptionsEndian Extr Intr 23 TCP2 Endian Register TcpendTCP2 Endian Register Tcpend Field Descriptions Endianextr24 TCP2 Error Register Tcperr TCP2 Error Register Tcperr Field DescriptionsSubframe length TCP2 Status Register Tcpstat Field Descriptions 25 TCP2 Status Register TcpstatTcpstate Waiting for RAM extrinsic memory 0 to be read Soft = 26 TCP2 Emulation Register TcpemuTCP2 Emulation Register Tcpemu Field Descriptions Soft FreeEndianness Data Memory for SystematicData Memory 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116EN = 0 Big-Endian Mode Rate = 1/4 EN = 0 Big-Endian Mode Rate = 3/4 Hard Decision DataData Hard Decisions in DSP MemoryTcpendian Register for Endianness Manager HD1 HD0Interleaver Indexes in DSP Memory Tcpendian Programming RegisterEndianintr = Data Native Format DSP Memory FormatINTER0 INTER1 INTER2 INTER3 INTER3 INTER2 INTER1 INTER0Endianextr = Extrinsic DataExtrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 ArchitectureEXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 MAP Unit Block Diagram Sub-block and Sliding Window SegmentationSubframe Segmentation SP mode only Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and WinrelReliability and Prolog Length Calculation Added Features Code RatesInput Sign Valid Re-Encode Symbols Used for ComparisonProgramming Log EquationEDMA3 Resources EDMA3 Parameters in Standalone SA ModeEDMA3 Parameters in Shared Processing SP Mode 1 TCP2 Dedicated EDMA3 ResourcesEDMA3 Programming Programming Standalone SA ModeInput Configuration Parameters Transfer Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Input Configurations Parameters Programming Output Parameters TransferInter TCPIC0 Programming Shared-Processing SP ModeOpmod TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Events Generation Output ParametersInter TCPIC0 Inter = Outf Errors Debug Mode Pause After Each MapErrors and Status Error Status ERRUnexpected Frame Length F Unexpected Signal to Noise Ratio SNRUnexpected Memory Access ACC Unexpected Prolog Length PStatus 13.2.14 TCP2 SNR Status snrexceed 13.2.12 TCP2 Active State Status Activestate13.2.13 TCP2 Active Iteration Status Activeiter 13.2.15 TCP2 CRC Status CrcpassDSP Products ApplicationsRfid
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