Texas Instruments TMS320C6457 DSP manual TMS320C6457 Turbo-Decoder Coprocessor, Features

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User's Guide

SPRUGK1–March 2009

TMS320C6457 Turbo-Decoder Coprocessor 2

Channel decoding of high bit-rate data channels found in third-generation (3G) cellular standards requires decoding of turbo-encoded data. The turbo-decoder coprocessor (TCP2) in some of the digital signal processor (DSPs) of the TMS320C6000E DSP family has been designed to perform this operation for IS2000 and 3GPP wireless standards. This document describes the operation and programming of the TCP2.

1Features

The TCP2 provides:

∙High performance:

–Very-low-processing delay because of the highly paralleled architecture allowing 8 iterations of a 2 Mbps 3GPP channel to be decoded in less than 1.2 ms and an IS2000 channel in less than 1.2 ms.

–Processing delay can be further reduced by enabling a stopping criteria algorithm while achieving optimal BER performance.

–TCP2 and the DSP can run full speed in parallel.

∙System cost optimization:

–Reduces board space and power consumption by performing on-chip turbo-decoding.

–Communication between the DSP and the TCP2 is performed through a high performance DMA engine, the enhanced DMA (EDMA3).

–TCP2 uses its own optimized memories, reducing system memory overhead and yielding higher overall performance.

–Increased programmability.

–Power efficient and module power-saver capabilities.

∙High flexibility to cope with standard evolutions:

–Accepts all IS2000, 3GPP rates, and polynomials.

–Accepts any frame length from 40 (3GPP minimum frame size) up to 20730 for standalone processing. Frame sizes greater than 20730 can be processed by breaking them up into smaller subframes for processing in shared processing mode.

–Supports all interleaver combinations via interleaver table.

–Frees-up DSP resources.

∙Improvements over TCP:

–Standalone mode frame length increased from 5114 to 20730.

–Code rates 1/2,1/3,1/4 and 1/5 (other rates via de-puncturing may be achieved).

–Prolog reduction.

–Cyclic redundancy check (CRC) stopping criteria.

–Channel re-encoding.

–Max-Log Maximum a Posteriori (MAP) option added to TCP2 (Max*-Log MAP still available).

–Input sign programmable.

–Debug mode added to allow pausing after each MAP.

–Decision ordering programmable as MSB first or LSB first.

–Extrinsic scaling added for Max-Log MAP.

SPRUGK1–March 2009

TMS320C6457 Turbo-Decoder Coprocessor 2

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments TrademarksTMS320C6457 Turbo-Decoder Coprocessor FeaturesIntroduction GPP and IS2000 Turbo-Encoder Block DiagramOverview GPP and IS2000 Turbo-Decoder Block DiagramTCP2 Mode Standalone SA ModeSystematic and Parity Data Input Data FormatSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Stopping Criteria Output Decision Data FormatInterleaver Indexes Interleaver DataStopping Test Unit SNR Threshold TerminationCRC Termination Parameter Termination Shared-Processing SP ModeMaximum Iterations Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Output Data Format Priori DataRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 TCP2 Registers RegistersTCP2 RAMs NameRegisters Peripheral Identification Register PID Field Descriptions Peripheral Identification Register PIDBit Field DescriptionBit Field Value Description TCP2 Input Configuration Register 0 TCPIC0TCP2 Input Configuration Register 2 TCPIC2 TCP2 Input Configuration Register 1 TCPIC1SNR MaxitTCP2 Input Configuration Register 3 TCPIC3 TCP2 Input Configuration Register 4 TCPIC4 CrciterpassCrclen Tail Symbols TCP2 Input Configuration Register 5 TCPIC5CRC Examples CrcpolyTAIL1 TCP2 Input Configuration Register 6 TCPIC6TAIL2 10 TCP2 Input Configuration Register 7 TCPIC7TAIL3 11 TCP2 Input Configuration Register 8 TCPIC8TAIL4 12 TCP2 Input Configuration Register 9 TCPIC913 TCP2 Input Configuration Register 10 TCPIC10 14 TCP2 Input Configuration Register 11 TCPIC11TAIL5 TCP2 Input Configuration Register 11 TCPIC11 16 TCP2 Input Configuration Register 13 TCPIC13 15 TCP2 Input Configuration Register 12 TCPIC12EXTSCALE03 EXTSCALE47EXTSCALE811 17 TCP2 Input Configuration Register 14 TCPIC14Extrinsic Scale Registers 18 TCP2 Input Configuration Register 15 TCPIC15EXTSCALE1215 Iteration Number20 TCP2 Output Parameter Register 1 TCPOUT1 19 TCP2 Output Parameter Register 0 TCPOUT0TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions22 TCP2 Execution Register Tcpexe 21 TCP2 Output Parameter Register 2 TCPOUT2TCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions TCP2 Execution Register Tcpexe Field DescriptionsTCP2 Endian Register Tcpend Field Descriptions 23 TCP2 Endian Register TcpendEndian Extr Intr EndianextrTCP2 Error Register Tcperr Field Descriptions 24 TCP2 Error Register TcperrSubframe length 25 TCP2 Status Register Tcpstat TCP2 Status Register Tcpstat Field DescriptionsTcpstate Waiting for RAM extrinsic memory 0 to be read TCP2 Emulation Register Tcpemu Field Descriptions 26 TCP2 Emulation Register TcpemuSoft = Soft FreeData Memory for Systematic Endianness6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 Data MemoryEN = 0 Big-Endian Mode Rate = 1/4 Hard Decision Data EN = 0 Big-Endian Mode Rate = 3/4Tcpendian Register for Endianness Manager Hard Decisions in DSP MemoryData HD1 HD0Endianintr = Tcpendian Programming RegisterInterleaver Indexes in DSP Memory Data Native Format DSP Memory FormatINTER3 INTER2 INTER1 INTER0 INTER0 INTER1 INTER2 INTER3Extrinsic Data Endianextr =Extrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = Architecture EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0EXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 Sub-block and Sliding Window Segmentation MAP Unit Block DiagramExamples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Subframe Segmentation SP mode onlyReliability and Prolog Length Calculation Code Rates Added FeaturesProgramming Valid Re-Encode Symbols Used for ComparisonInput Sign Log EquationEDMA3 Parameters in Shared Processing SP Mode EDMA3 Parameters in Standalone SA ModeEDMA3 Resources 1 TCP2 Dedicated EDMA3 ResourcesInput Configuration Parameters Transfer Programming Standalone SA ModeEDMA3 Programming Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Output Parameters Transfer Input Configurations Parameters ProgrammingOpmod TCPIC0 Programming Shared-Processing SP ModeInter TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Output Parameters Events GenerationInter TCPIC0 Inter = Outf Errors and Status Debug Mode Pause After Each MapErrors Error Status ERRUnexpected Memory Access ACC Unexpected Signal to Noise Ratio SNRUnexpected Frame Length F Unexpected Prolog Length PStatus 13.2.13 TCP2 Active Iteration Status Activeiter 13.2.12 TCP2 Active State Status Activestate13.2.14 TCP2 SNR Status snrexceed 13.2.15 TCP2 CRC Status CrcpassProducts Applications DSPRfid
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