Texas Instruments TMS320C6457 DSP manual Architecture, EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0

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Architecture

7.1.4.2ENDIAN_EXTR = 0

If ENDIAN_EXTR = 0, data are saved in word format (32 bits) in the DSP (see Table 39).

Table 39. Extrinsic in DSP Memory (ENDIAN_EXTR =

0)

Address (hex bytes)	Data
Base	EXT3
Base + 1	EXT2
Base + 2	EXT1
Base + 3	EXT0
Base + 4	EXT7
Base + 5	EXT6
Base + 6	EXT5
Base + 7	EXT4

Figure 92. Extrinsic in DSP Memory (ENDIAN_EXTR = 0)

Endian_Extr=0

Base 0

Base 7

Memory

XT3

XT2

XT1

XT0

XT7

XT6

XT5

XT4

EDMA3

	XT3	XT2	XT1	XT0	XT7	XT6	XT5	XT4
	XT3	XT2	XT1	XT0	XT7	XT6	XT5	XT4

	63							0

TCP

Endianness manager

Kernel

	XT7	XT6	XT5	XT4	XT3	XT2	XT1	XT0
	XT7	XT6	XT5	XT4	XT3	XT2	XT1	XT0

	63							0

They have to be swapped as described in Figure 93 and Figure 94.

Figure 93. Data Source - Kernel (ENDIAN_EXTR = 0)

63:56	55:48	47:40	39:32	31:24	23:16	15:8	7:0
EXT7	EXT6	EXT5	EXT4	EXT3	EXT2	EXT1	EXT0

Figure 94. Data Destination - EDMA3 (ENDIAN_EXTR = 0)

63:56	55:48	47:40	39:32	31:24	23:16	15:8	7:0
EXT3	EXT2	EXT1	EXT0	EXT7	EXT6	EXT5	EXT4

8Architecture

The TCP2 processing unit (MAP unit) is shown in Figure 95. The beta kernel performs the MAP algorithm backward recursion and produces beta probabilities stored in the beta RAM. The alpha kernel performs the forward recursion producing alpha probabilities, and the extrinsic block computes the extrinsics to be stored in the extrinsics memory.

The processing unit implements the Max* Log-MAP algorithm using a sliding window technique that allows parallel processing and reduces dramatic memory requirements.

SPRUGK1–March 2009

TMS320C6457 Turbo-Decoder Coprocessor 2

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Trademarks About This ManualNotational Conventions Related Documentation From Texas InstrumentsTMS320C6457 Turbo-Decoder Coprocessor FeaturesIntroduction GPP and IS2000 Turbo-Encoder Block DiagramOverview GPP and IS2000 Turbo-Decoder Block DiagramTCP2 Mode Standalone SA ModeSystematic and Parity Data Input Data FormatSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5EN = 0 Big-Endian Mode Rate = 1/4 Interleaver Data Output Decision Data FormatStopping Criteria Interleaver IndexesCRC Termination Stopping Test UnitSNR Threshold Termination Minimum Iterations Shared-Processing SP ModeParameter Termination Maximum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Rsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 Output Data FormatPriori Data Name RegistersTCP2 Registers TCP2 RAMsRegisters Description Peripheral Identification Register PIDPeripheral Identification Register PID Field Descriptions Bit FieldBit Field Value Description TCP2 Input Configuration Register 0 TCPIC0Maxit TCP2 Input Configuration Register 1 TCPIC1TCP2 Input Configuration Register 2 TCPIC2 SNRTCP2 Input Configuration Register 3 TCPIC3 Crclen TCP2 Input Configuration Register 4 TCPIC4Crciterpass Crcpoly TCP2 Input Configuration Register 5 TCPIC5Tail Symbols CRC ExamplesTAIL1 TCP2 Input Configuration Register 6 TCPIC6TAIL2 10 TCP2 Input Configuration Register 7 TCPIC7TAIL3 11 TCP2 Input Configuration Register 8 TCPIC8TAIL4 12 TCP2 Input Configuration Register 9 TCPIC9TAIL5 13 TCP2 Input Configuration Register 10 TCPIC1014 TCP2 Input Configuration Register 11 TCPIC11 TCP2 Input Configuration Register 11 TCPIC11 EXTSCALE47 15 TCP2 Input Configuration Register 12 TCPIC1216 TCP2 Input Configuration Register 13 TCPIC13 EXTSCALE03EXTSCALE811 17 TCP2 Input Configuration Register 14 TCPIC14Iteration Number 18 TCP2 Input Configuration Register 15 TCPIC15Extrinsic Scale Registers EXTSCALE1215TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions 19 TCP2 Output Parameter Register 0 TCPOUT020 TCP2 Output Parameter Register 1 TCPOUT1 TCP2 Output Parameter Register 0 TCPOUT0 Field DescriptionsTCP2 Execution Register Tcpexe Field Descriptions 21 TCP2 Output Parameter Register 2 TCPOUT222 TCP2 Execution Register Tcpexe TCP2 Output Parameter Register 2 TCPOUT2 Field DescriptionsEndianextr 23 TCP2 Endian Register TcpendTCP2 Endian Register Tcpend Field Descriptions Endian Extr IntrTCP2 Error Register Tcperr Field Descriptions 24 TCP2 Error Register TcperrSubframe length Tcpstate 25 TCP2 Status Register TcpstatTCP2 Status Register Tcpstat Field Descriptions Waiting for RAM extrinsic memory 0 to be read Soft Free 26 TCP2 Emulation Register TcpemuTCP2 Emulation Register Tcpemu Field Descriptions Soft =Data Memory for Systematic Endianness6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 Data MemoryEN = 0 Big-Endian Mode Rate = 1/4 Hard Decision Data EN = 0 Big-Endian Mode Rate = 3/4HD1 HD0 Hard Decisions in DSP MemoryTcpendian Register for Endianness Manager DataData Native Format DSP Memory Format Tcpendian Programming RegisterEndianintr = Interleaver Indexes in DSP MemoryINTER3 INTER2 INTER1 INTER0 INTER0 INTER1 INTER2 INTER3Extrinsic in DSP Memory Endianextr = Extrinsic DataEndianextr = Data Source Kernel Endianextr = EXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 ArchitectureEXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 Sub-block and Sliding Window Segmentation MAP Unit Block DiagramExamples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Subframe Segmentation SP mode onlyReliability and Prolog Length Calculation Code Rates Added FeaturesLog Equation Valid Re-Encode Symbols Used for ComparisonProgramming Input Sign1 TCP2 Dedicated EDMA3 Resources EDMA3 Parameters in Standalone SA ModeEDMA3 Parameters in Shared Processing SP Mode EDMA3 ResourcesSystematics and Parities Transfer Programming Standalone SA ModeInput Configuration Parameters Transfer EDMA3 ProgrammingInterleaver Indexes Transfer Hard-Decisions Transfer Output Parameters Transfer Input Configurations Parameters ProgrammingOutf TCPIC0 Programming Shared-Processing SP ModeOpmod TCPIC0 Inter TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Inter TCPIC0 Inter = Outf Output ParametersEvents Generation Error Status ERR Debug Mode Pause After Each MapErrors and Status ErrorsUnexpected Prolog Length P Unexpected Signal to Noise Ratio SNRUnexpected Memory Access ACC Unexpected Frame Length FStatus 13.2.15 TCP2 CRC Status Crcpass 13.2.12 TCP2 Active State Status Activestate13.2.13 TCP2 Active Iteration Status Activeiter 13.2.14 TCP2 SNR Status snrexceedRfid Products ApplicationsDSP