Texas Instruments TMS320C6457 DSP TCP2 Registers, TCP2 RAMs, Name Address Range Length

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Registers

6Registers

The TCP2 contains several memory-mapped registers accessible via the CPU, QDMA, and EDMA3. A peripheral-bus access is faster than an EDMA3-bus access for isolated accesses (typically when accessing control registers). EDMA3-bus accesses are intended to be used for EDMA3 transfers and are meant to provide maximum throughput to/from the TCP2.

The memory map is listed in Table 3, including all TCP2 memories (systematic and parity, interleaver, hard decisions, a priori, and extrinsic). All addresses provided are offset addresses. For the TCP2 base data address and TCP2 base control address, see the device-specific data manual.

Table 3. TCP2 Registers

TCP2 Data Offset	TCP2 Control	Register/Memory
Address	Offset Address	Abbreviation	Name	See
	0x00000	TCPPID	TCP Peripheral Identification Register	Section 6.1
0x00000		TCPIC0	TCP Input Configuration Register 0	Section 6.2
0x00004		TCPIC1	TCP Input Configuration Register 1	Section 6.3
0x00008		TCPIC2	TCP Input Configuration Register 2	Section 6.4
0x0000C		TCPIC3	TCP Input Configuration Register 3	Section 6.5
0x00010		TCPIC4	TCP Input Configuration Register 4	Section 6.6
0x00014		TCPIC5	TCP Input Configuration Register 5	Section 6.7
0x00018		TCPIC6	TCP Input Configuration Register 6	Section 6.8
0x0001C		TCPIC7	TCP Input Configuration Register 7	Section 6.10
0x00020		TCPIC8	TCP Input Configuration Register 8	Section 6.11
0x00024		TCPIC9	TCP Input Configuration Register 9	Section 6.12
0x00028		TCPIC10	TCP Input Configuration Register 10	Section 6.13
0x0002C		TCPIC11	TCP Input Configuration Register 11	Section 6.14
0x00030		TCPIC12	TCP Input Configuration Register 12	Section 6.15
0x00034		TCPIC13	TCP Input Configuration Register 13	Section 6.16
0x00038		TCPIC14	TCP Input Configuration Register 14	Section 6.17
0x0003C		TCPIC15	TCP Input Configuration Register 15	Section 6.18
0x00040		TCPOUT0	TCP Output Parameters Register 0	Section 6.19
0x00044		TCPOUT1	TCP Output Parameters Register 1	Section 6.20
0x00048		TCPOUT2	TCP Output Parameters Register 2	Section 6.21
	0x0004C	TCPEXE	TCP Execute Register	Section 6.22
	0x00050	TCPEND	TCP Endianness Register	Section 6.23
	0x00060	TCPERR	TCP Error Register	Section 6.24
	0x00068	TCPSTAT	TCP Status Register	Section 6.25
	0x00070	TCPEMU	TCP Emulation Register	Section 6.26

Table 4. TCP2 RAMs

TCP2 Data Offset	Register/Memory
Address	Abbreviation	Name	Address Range	Length
0x10000	X0	Data/Sys and Parity Memory	0x10000-0x243FF	0x00014400
0x30000	W0	Extrinsic Mem 0	0x30000-0x351FF	0x00005100
0x40000	W1	Extrinsic Mem 1	0x40000-0x451FF	0x00005100
0x50000	I0	Interleaver Memory	0x50000-0x5a1FF	0x0000A200
0x60000	O0	Output/Decision Memory	0x60000-0x60a7F	0x00000A20
0x70000	S0	Scratch Pad Memory	0x70000-0x70aFF	0x000006E0
0x80000	T0	Beta State Memory	0x80000-0x80FFF	0x00000A00
0x90000	C0	CRC Memory	0x90000-0x90FFF	0x000001C0
SPRUGK1–March 2009			TMS320C6457 Turbo-Decoder Coprocessor 2		25

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments TrademarksTMS320C6457 Turbo-Decoder Coprocessor FeaturesIntroduction GPP and IS2000 Turbo-Encoder Block DiagramOverview GPP and IS2000 Turbo-Decoder Block DiagramTCP2 Mode Standalone SA ModeSystematic and Parity Data Input Data FormatSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Stopping Criteria Output Decision Data FormatInterleaver Indexes Interleaver DataSNR Threshold Termination Stopping Test UnitCRC Termination Parameter Termination Shared-Processing SP ModeMaximum Iterations Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Priori Data Output Data FormatRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 TCP2 Registers RegistersTCP2 RAMs NameRegisters Peripheral Identification Register PID Field Descriptions Peripheral Identification Register PIDBit Field DescriptionBit Field Value Description TCP2 Input Configuration Register 0 TCPIC0TCP2 Input Configuration Register 2 TCPIC2 TCP2 Input Configuration Register 1 TCPIC1SNR MaxitTCP2 Input Configuration Register 3 TCPIC3 Crciterpass TCP2 Input Configuration Register 4 TCPIC4Crclen Tail Symbols TCP2 Input Configuration Register 5 TCPIC5CRC Examples CrcpolyTAIL1 TCP2 Input Configuration Register 6 TCPIC6TAIL2 10 TCP2 Input Configuration Register 7 TCPIC7TAIL3 11 TCP2 Input Configuration Register 8 TCPIC8TAIL4 12 TCP2 Input Configuration Register 9 TCPIC914 TCP2 Input Configuration Register 11 TCPIC11 13 TCP2 Input Configuration Register 10 TCPIC10TAIL5 TCP2 Input Configuration Register 11 TCPIC11 16 TCP2 Input Configuration Register 13 TCPIC13 15 TCP2 Input Configuration Register 12 TCPIC12EXTSCALE03 EXTSCALE47EXTSCALE811 17 TCP2 Input Configuration Register 14 TCPIC14Extrinsic Scale Registers 18 TCP2 Input Configuration Register 15 TCPIC15EXTSCALE1215 Iteration Number20 TCP2 Output Parameter Register 1 TCPOUT1 19 TCP2 Output Parameter Register 0 TCPOUT0TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions22 TCP2 Execution Register Tcpexe 21 TCP2 Output Parameter Register 2 TCPOUT2TCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions TCP2 Execution Register Tcpexe Field DescriptionsTCP2 Endian Register Tcpend Field Descriptions 23 TCP2 Endian Register TcpendEndian Extr Intr EndianextrTCP2 Error Register Tcperr Field Descriptions 24 TCP2 Error Register TcperrSubframe length TCP2 Status Register Tcpstat Field Descriptions 25 TCP2 Status Register TcpstatTcpstate Waiting for RAM extrinsic memory 0 to be read TCP2 Emulation Register Tcpemu Field Descriptions 26 TCP2 Emulation Register TcpemuSoft = Soft FreeData Memory for Systematic Endianness6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 Data MemoryEN = 0 Big-Endian Mode Rate = 1/4 Hard Decision Data EN = 0 Big-Endian Mode Rate = 3/4Tcpendian Register for Endianness Manager Hard Decisions in DSP MemoryData HD1 HD0Endianintr = Tcpendian Programming RegisterInterleaver Indexes in DSP Memory Data Native Format DSP Memory FormatINTER3 INTER2 INTER1 INTER0 INTER0 INTER1 INTER2 INTER3Endianextr = Extrinsic DataExtrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 ArchitectureEXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 Sub-block and Sliding Window Segmentation MAP Unit Block DiagramExamples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Subframe Segmentation SP mode onlyReliability and Prolog Length Calculation Code Rates Added FeaturesProgramming Valid Re-Encode Symbols Used for ComparisonInput Sign Log EquationEDMA3 Parameters in Shared Processing SP Mode EDMA3 Parameters in Standalone SA ModeEDMA3 Resources 1 TCP2 Dedicated EDMA3 ResourcesInput Configuration Parameters Transfer Programming Standalone SA ModeEDMA3 Programming Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Output Parameters Transfer Input Configurations Parameters ProgrammingOpmod TCPIC0 Programming Shared-Processing SP ModeInter TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Events Generation Output ParametersInter TCPIC0 Inter = Outf Errors and Status Debug Mode Pause After Each MapErrors Error Status ERRUnexpected Memory Access ACC Unexpected Signal to Noise Ratio SNRUnexpected Frame Length F Unexpected Prolog Length PStatus 13.2.13 TCP2 Active Iteration Status Activeiter 13.2.12 TCP2 Active State Status Activestate13.2.14 TCP2 SNR Status snrexceed 13.2.15 TCP2 CRC Status CrcpassDSP Products ApplicationsRfid