Texas Instruments TMS320C6457 DSP manual Overview, GPP and IS2000 Turbo-Decoder Block Diagram

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Overview

uses the corresponding estimates from the other decoder as a priori likelihood. The a priori information is seen as beforehand knowledge, meaning that some messages are more likely to occur than others. A posteriori information adds to the a priori information the knowledge gained by the decoding.

The uncoded information bits (corrupted by the noisy channel) are available to each decoder to initialize the a priori likelihoods. The decoders use the Maximum a Posteriori (MAP) bitwise decoding algorithm that requires the same number of states as the well known Viterbi algorithm. The turbo decoder iterates between the outputs of the two constituent decoders until it reaches satisfactory convergence. The final output is a hard-quantized version of the likelihood estimates of the decoders.

Figure 2. 3GPP and IS2000 Turbo-Decoder Block Diagram

Decoded bits

 

Hard

 

 

 

decisions

 

 

 

calculation

 

 

 

A priori

 

 

 

information

Deinterleave

 

 

 

 

 

 

 

A priori

 

Received parities

 

information

 

A & B symbols

Interleave

MAP2

 

MAP1

 

Received systematics

 

 

 

X symbols

 

 

 

Received parities A’ & B ’ symbols

Received systematics

 

 

 

X’ symbols

 

 

Interleave

 

3

Overview

 

 

The DSP controls the operation of the TCP2 (Figure 3) using memory-mapped registers. The DSP typically sends and receives data using synchronized EDMA3 transfers through the 64-bit EDMA3 bus. The TCP2 sends two synchronization events to the EDMA3: a receive event (TCPREVT) and a transmit event (TCPXEVT).

The processing unit can implement the Max*-Log-MAP or Max-Log-MAP approximations of the BCJR algorithm and is selected with the E_MAX_STAR bit of the TCPIC3 register. (See L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal decoding of linear codes for minimizing symbol error rate",. IEEE Trans. Inform.Theory, vol. IT.20, pp. 284.287, Mar. 1974 and P. Robertson, E. Villebrun, and P. Hoeher, "A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain", in Proc. 1996 IEEE Int. Conf. on Communications (Seattle, WA), June 1995, vol. 2, pp. 1009-1013.)

The TCP2 has two fundamental modes: standalone (SA) and shared processing (SP).

In SA mode, the TCP2 iterates a given number of times and outputs hard decisions. In SP mode, the TCP2 executes a single MAP decode and outputs extrinsic information (soft information). SA mode is typically used for frame sizes up to 20730. SP mode must be used for frames strictly larger than 20730. Table 1 describes which mode to use depending on the frame size.

The TCP2 input data corresponds to channel log-likelihood ratios scaled on 6 bits, while the TCP2 output data to hard-decisions (SA mode) or extrinsics (SP mode) scaled on 7 bits.

SPRUGK1–March 2009

TMS320C6457 Turbo-Decoder Coprocessor 2

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Trademarks About This ManualNotational Conventions Related Documentation From Texas InstrumentsTMS320C6457 Turbo-Decoder Coprocessor FeaturesIntroduction GPP and IS2000 Turbo-Encoder Block DiagramOverview GPP and IS2000 Turbo-Decoder Block DiagramTCP2 Mode Standalone SA ModeSystematic and Parity Data Input Data FormatSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5EN = 0 Big-Endian Mode Rate = 1/4 Interleaver Data Output Decision Data FormatStopping Criteria Interleaver IndexesCRC Termination Stopping Test UnitSNR Threshold Termination Minimum Iterations Shared-Processing SP ModeParameter Termination Maximum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Rsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 Output Data FormatPriori Data Name RegistersTCP2 Registers TCP2 RAMsRegisters Description Peripheral Identification Register PIDPeripheral Identification Register PID Field Descriptions Bit FieldBit Field Value Description TCP2 Input Configuration Register 0 TCPIC0Maxit TCP2 Input Configuration Register 1 TCPIC1TCP2 Input Configuration Register 2 TCPIC2 SNRTCP2 Input Configuration Register 3 TCPIC3 Crclen TCP2 Input Configuration Register 4 TCPIC4Crciterpass Crcpoly TCP2 Input Configuration Register 5 TCPIC5Tail Symbols CRC ExamplesTAIL1 TCP2 Input Configuration Register 6 TCPIC6TAIL2 10 TCP2 Input Configuration Register 7 TCPIC7TAIL3 11 TCP2 Input Configuration Register 8 TCPIC8TAIL4 12 TCP2 Input Configuration Register 9 TCPIC9TAIL5 13 TCP2 Input Configuration Register 10 TCPIC1014 TCP2 Input Configuration Register 11 TCPIC11 TCP2 Input Configuration Register 11 TCPIC11 EXTSCALE47 15 TCP2 Input Configuration Register 12 TCPIC1216 TCP2 Input Configuration Register 13 TCPIC13 EXTSCALE03EXTSCALE811 17 TCP2 Input Configuration Register 14 TCPIC14Iteration Number 18 TCP2 Input Configuration Register 15 TCPIC15Extrinsic Scale Registers EXTSCALE1215TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions 19 TCP2 Output Parameter Register 0 TCPOUT020 TCP2 Output Parameter Register 1 TCPOUT1 TCP2 Output Parameter Register 0 TCPOUT0 Field DescriptionsTCP2 Execution Register Tcpexe Field Descriptions 21 TCP2 Output Parameter Register 2 TCPOUT222 TCP2 Execution Register Tcpexe TCP2 Output Parameter Register 2 TCPOUT2 Field DescriptionsEndianextr 23 TCP2 Endian Register TcpendTCP2 Endian Register Tcpend Field Descriptions Endian Extr IntrTCP2 Error Register Tcperr Field Descriptions 24 TCP2 Error Register TcperrSubframe length Tcpstate 25 TCP2 Status Register TcpstatTCP2 Status Register Tcpstat Field Descriptions Waiting for RAM extrinsic memory 0 to be read Soft Free 26 TCP2 Emulation Register TcpemuTCP2 Emulation Register Tcpemu Field Descriptions Soft =Data Memory for Systematic Endianness6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 Data MemoryEN = 0 Big-Endian Mode Rate = 1/4 Hard Decision Data EN = 0 Big-Endian Mode Rate = 3/4HD1 HD0 Hard Decisions in DSP MemoryTcpendian Register for Endianness Manager DataData Native Format DSP Memory Format Tcpendian Programming RegisterEndianintr = Interleaver Indexes in DSP MemoryINTER3 INTER2 INTER1 INTER0 INTER0 INTER1 INTER2 INTER3Extrinsic in DSP Memory Endianextr = Extrinsic DataEndianextr = Data Source Kernel Endianextr = EXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 ArchitectureEXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 Sub-block and Sliding Window Segmentation MAP Unit Block DiagramExamples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Subframe Segmentation SP mode onlyReliability and Prolog Length Calculation Code Rates Added FeaturesLog Equation Valid Re-Encode Symbols Used for ComparisonProgramming Input Sign1 TCP2 Dedicated EDMA3 Resources EDMA3 Parameters in Standalone SA ModeEDMA3 Parameters in Shared Processing SP Mode EDMA3 ResourcesSystematics and Parities Transfer Programming Standalone SA ModeInput Configuration Parameters Transfer EDMA3 ProgrammingInterleaver Indexes Transfer Hard-Decisions Transfer Output Parameters Transfer Input Configurations Parameters ProgrammingOutf TCPIC0 Programming Shared-Processing SP ModeOpmod TCPIC0 Inter TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Inter TCPIC0 Inter = Outf Output ParametersEvents Generation Error Status ERR Debug Mode Pause After Each MapErrors and Status ErrorsUnexpected Prolog Length P Unexpected Signal to Noise Ratio SNRUnexpected Memory Access ACC Unexpected Frame Length FStatus 13.2.15 TCP2 CRC Status Crcpass 13.2.12 TCP2 Active State Status Activestate13.2.13 TCP2 Active Iteration Status Activeiter 13.2.14 TCP2 SNR Status snrexceedRfid Products ApplicationsDSP
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