Texas Instruments TMS320C6457 DSP manual Unexpected Frame Length F, Unexpected Prolog Length P

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Errors and Status

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13.1.2Unexpected Frame Length: F

The F bit is set to 1 if the programmed frame length is strictly smaller than 40 or is strictly greater than 20730 for standalone mode.

The F bit is set to 1 if the programmed frame length has the following values for shared processing mode:

1.Frame length < 256 or frame length > 20480 or (frame length)%256 != 0 if opmode = 1 or 2.

2.Frame length < 128 or frame length > 20480 if opmode = 3.

13.1.3Unexpected Prolog Length: P

The P bit is set to 1 if the specified prolog length is strictly greater than 48. Values smaller than 4 are ignored by the hardware and 24 is used.

13.1.4Unexpected Subframe Length: SF

The SF bit is set to 1 if the specified subframe length is strictly greater than 20480 in shared processing mode.

13.1.5Unexpected Reliability Length: R

The R bit is set to 1 if the specified reliability length minus 1 is strictly smaller than 40 or greater than 128 in SA mode.

The R bit is set to 1 if the specified reliability length is not equal to 128 in SP mode if opmode = 1 or 2.

The R bit is set to 1 if the specified reliability length is less than 65 in SP mode if opmode = 3.

13.1.6Unexpected Signal to Noise Ratio: SNR

The SNR bit is set to 1 if the signal to noise ratio threshold is greater than 100.

13.1.7Unexpected Interleaver Table Load: INT

The INT bit is set to 1 if loading an interleaver table has been requested in SP mode.

13.1.8Unexpected Output Parameters Load: OP

The OP bit is set to 1 if loading the output parameters has been requested in SP mode.

13.1.9Unexpected Memory Access: ACC

The ACC bit is set to 1 when an unexpected memory access occurs. This can be used to spot any EDMA3 programming issues. This can occur when:

∙TCP2 is waiting for input configuration parameters state and memory access to any TCP2 memory but the interleaver memory is performed

∙TCP2 is waiting for systematics and parities state and memory access to any TCP2 memory other than the TCPINTER memory

∙TCP2 is waiting for a prioris state and memory access to any TCP2 memory other than the TCPAP memory

∙TCP2 is waiting for extrinsics state and memory access to any TCP2 memory other than the TCPEXT memory

∙TCP2 is waiting for hard decisions state and memory access to any TCP2 memory other than the TCPHD memory

∙TCP2 is waiting for output parameters state and memory access to any TCP2 memory

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TMS320C6457 Turbo-Decoder Coprocessor 2

SPRUGK1–March 2009

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables About This Manual Notational ConventionsRelated Documentation From Texas Instruments TrademarksFeatures TMS320C6457 Turbo-Decoder CoprocessorGPP and IS2000 Turbo-Encoder Block Diagram IntroductionGPP and IS2000 Turbo-Decoder Block Diagram OverviewStandalone SA Mode TCP2 ModeInput Data Format Systematic and Parity DataRsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Output Decision Data Format Stopping CriteriaInterleaver Indexes Interleaver DataSNR Threshold Termination Stopping Test UnitCRC Termination Shared-Processing SP Mode Parameter TerminationMaximum Iterations Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Priori Data Output Data FormatRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 Registers TCP2 RegistersTCP2 RAMs NameRegisters Peripheral Identification Register PID Peripheral Identification Register PID Field DescriptionsBit Field DescriptionTCP2 Input Configuration Register 0 TCPIC0 Bit Field Value DescriptionTCP2 Input Configuration Register 1 TCPIC1 TCP2 Input Configuration Register 2 TCPIC2SNR MaxitTCP2 Input Configuration Register 3 TCPIC3 Crciterpass TCP2 Input Configuration Register 4 TCPIC4Crclen TCP2 Input Configuration Register 5 TCPIC5 Tail SymbolsCRC Examples CrcpolyTCP2 Input Configuration Register 6 TCPIC6 TAIL110 TCP2 Input Configuration Register 7 TCPIC7 TAIL211 TCP2 Input Configuration Register 8 TCPIC8 TAIL312 TCP2 Input Configuration Register 9 TCPIC9 TAIL414 TCP2 Input Configuration Register 11 TCPIC11 13 TCP2 Input Configuration Register 10 TCPIC10TAIL5 TCP2 Input Configuration Register 11 TCPIC11 15 TCP2 Input Configuration Register 12 TCPIC12 16 TCP2 Input Configuration Register 13 TCPIC13EXTSCALE03 EXTSCALE4717 TCP2 Input Configuration Register 14 TCPIC14 EXTSCALE81118 TCP2 Input Configuration Register 15 TCPIC15 Extrinsic Scale RegistersEXTSCALE1215 Iteration Number19 TCP2 Output Parameter Register 0 TCPOUT0 20 TCP2 Output Parameter Register 1 TCPOUT1TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions21 TCP2 Output Parameter Register 2 TCPOUT2 22 TCP2 Execution Register TcpexeTCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions TCP2 Execution Register Tcpexe Field Descriptions23 TCP2 Endian Register Tcpend TCP2 Endian Register Tcpend Field DescriptionsEndian Extr Intr Endianextr24 TCP2 Error Register Tcperr TCP2 Error Register Tcperr Field DescriptionsSubframe length TCP2 Status Register Tcpstat Field Descriptions 25 TCP2 Status Register TcpstatTcpstate Waiting for RAM extrinsic memory 0 to be read 26 TCP2 Emulation Register Tcpemu TCP2 Emulation Register Tcpemu Field DescriptionsSoft = Soft FreeEndianness Data Memory for SystematicData Memory 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116EN = 0 Big-Endian Mode Rate = 1/4 EN = 0 Big-Endian Mode Rate = 3/4 Hard Decision DataHard Decisions in DSP Memory Tcpendian Register for Endianness ManagerData HD1 HD0Tcpendian Programming Register Endianintr =Interleaver Indexes in DSP Memory Data Native Format DSP Memory FormatINTER0 INTER1 INTER2 INTER3 INTER3 INTER2 INTER1 INTER0Endianextr = Extrinsic DataExtrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 ArchitectureEXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 MAP Unit Block Diagram Sub-block and Sliding Window SegmentationSubframe Segmentation SP mode only Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and WinrelReliability and Prolog Length Calculation Added Features Code RatesValid Re-Encode Symbols Used for Comparison ProgrammingInput Sign Log EquationEDMA3 Parameters in Standalone SA Mode EDMA3 Parameters in Shared Processing SP ModeEDMA3 Resources 1 TCP2 Dedicated EDMA3 ResourcesProgramming Standalone SA Mode Input Configuration Parameters TransferEDMA3 Programming Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Input Configurations Parameters Programming Output Parameters TransferProgramming Shared-Processing SP Mode Opmod TCPIC0Inter TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Events Generation Output ParametersInter TCPIC0 Inter = Outf Debug Mode Pause After Each Map Errors and StatusErrors Error Status ERRUnexpected Signal to Noise Ratio SNR Unexpected Memory Access ACCUnexpected Frame Length F Unexpected Prolog Length PStatus 13.2.12 TCP2 Active State Status Activestate 13.2.13 TCP2 Active Iteration Status Activeiter13.2.14 TCP2 SNR Status snrexceed 13.2.15 TCP2 CRC Status CrcpassDSP Products ApplicationsRfid
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