Texas Instruments TMS320C6457 DSP manual 26 TCP2 Emulation Register Tcpemu, Soft =, Soft Free

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Registers

6.26 TCP2 Emulation Register (TCPEMU)

In emulation mode, the access to TCP2 memories can be done in read or write. TCP2 supports emulation mode. Emulation support helps in system debug. Emulation modes are achieved with the programmable SOFT and FREE bits in the TCP2 Emulation Register (TCPEMU) at the configuration bus address 0x00070. The TCP2 emulation register (TCPEMU) is shown in Figure 56 and described in Table 31.

Figure 56. TCP2 Emulation Register (TCPEMU)

31

 

 

 

 

16

 

 

 

Reserved

 

 

 

 

 

R/W-0

 

 

15

 

 

2

1

0

 

 

 

Reserved

SOFT

FREE

 

 

 

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

 

Table 31. TCP2 Emulation Register (TCPEMU) Field Descriptions

 

 

Bit

Field

Value

Description

 

 

31-2

Reserved

0

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

1

SOFT

 

SOFT bit

 

 

 

 

0

Emulation halt at either end of MAP decode or at end of decode prior to last XEVT. Stop at the end

 

 

 

of MAP decode has priority.

 

 

 

 

1

Emulation halt at end of decode prior to last XEVT

 

 

0

FREE

 

FREE bit

 

 

 

 

0

Soft emulation bit takes effect

 

 

 

 

1

TCP2 ignores emulation halt and runs to completion

 

 

The FREE and SOFT bits are designed to enable a flexible method of how the TCP2 is operated during an emulation halt of the CPU. The FREE bit determines if an emulation halt of the CPU will halt the TCP2 at all. If the FREE bit is set, and an emulation halt of the CPU occurs, the TCP2 will continue processing normally. If the FREE bit is cleared, and an emulation halt of the CPU occurs, then TCP2 will be halted in a manner determined by the SOFT bits setting. Note that when FREE = 1, SOFT has no effect.

Given that FREE = 0, and an emulation halt of the CPU occurs, the TCP2 will halt as follows based on the setting of SOFT bit.

SOFT = 0:

Emulation halt uses TCP2 debug mode. Any current MAP processing must complete before entering the emulation mode.

Current data transfer on the bus should complete and pending read/write requests to/from CPU/DMA should complete before emulation halt. If an active output event(TCPREVT/TCPXEVT) is output before this emulation halt, it should service that request before going into a suspend state. If an active MAP is processing before this emulation halt, TCP2 should service that request before going into a suspend state. TCP2 will pause after each MAP processing. No new read/write events to CPU or DMA should be generated. Any ongoing CPU or DMA read/write services to TCP2 should complete. The TCP2 will restart from the halt state and it will run to normal completion until next emulation halt.

SOFT = 1:

Current data transfer on the bus should complete and pending read/write requests to/from CPU/DMA should complete before emulation halt. If an active frame is processing before this emulation halt, it should service all requests before going into suspend state. Any ongoing CPU or DMA read/write services to TCP2 should complete. Frame processing should complete.

SPRUGK1–March 2009

TMS320C6457 Turbo-Decoder Coprocessor 2

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments TrademarksTMS320C6457 Turbo-Decoder Coprocessor FeaturesIntroduction GPP and IS2000 Turbo-Encoder Block DiagramOverview GPP and IS2000 Turbo-Decoder Block DiagramTCP2 Mode Standalone SA ModeSystematic and Parity Data Input Data FormatSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Stopping Criteria Output Decision Data FormatInterleaver Indexes Interleaver DataSNR Threshold Termination Stopping Test UnitCRC Termination Parameter Termination Shared-Processing SP ModeMaximum Iterations Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Priori Data Output Data FormatRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 TCP2 Registers RegistersTCP2 RAMs NameRegisters Peripheral Identification Register PID Field Descriptions Peripheral Identification Register PIDBit Field DescriptionBit Field Value Description TCP2 Input Configuration Register 0 TCPIC0TCP2 Input Configuration Register 2 TCPIC2 TCP2 Input Configuration Register 1 TCPIC1SNR MaxitTCP2 Input Configuration Register 3 TCPIC3 Crciterpass TCP2 Input Configuration Register 4 TCPIC4Crclen Tail Symbols TCP2 Input Configuration Register 5 TCPIC5CRC Examples CrcpolyTAIL1 TCP2 Input Configuration Register 6 TCPIC6TAIL2 10 TCP2 Input Configuration Register 7 TCPIC7TAIL3 11 TCP2 Input Configuration Register 8 TCPIC8TAIL4 12 TCP2 Input Configuration Register 9 TCPIC914 TCP2 Input Configuration Register 11 TCPIC11 13 TCP2 Input Configuration Register 10 TCPIC10TAIL5 TCP2 Input Configuration Register 11 TCPIC11 16 TCP2 Input Configuration Register 13 TCPIC13 15 TCP2 Input Configuration Register 12 TCPIC12EXTSCALE03 EXTSCALE47EXTSCALE811 17 TCP2 Input Configuration Register 14 TCPIC14Extrinsic Scale Registers 18 TCP2 Input Configuration Register 15 TCPIC15EXTSCALE1215 Iteration Number20 TCP2 Output Parameter Register 1 TCPOUT1 19 TCP2 Output Parameter Register 0 TCPOUT0TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions22 TCP2 Execution Register Tcpexe 21 TCP2 Output Parameter Register 2 TCPOUT2TCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions TCP2 Execution Register Tcpexe Field DescriptionsTCP2 Endian Register Tcpend Field Descriptions 23 TCP2 Endian Register TcpendEndian Extr Intr EndianextrTCP2 Error Register Tcperr Field Descriptions 24 TCP2 Error Register TcperrSubframe length TCP2 Status Register Tcpstat Field Descriptions 25 TCP2 Status Register TcpstatTcpstate Waiting for RAM extrinsic memory 0 to be read TCP2 Emulation Register Tcpemu Field Descriptions 26 TCP2 Emulation Register TcpemuSoft = Soft FreeData Memory for Systematic Endianness6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 Data MemoryEN = 0 Big-Endian Mode Rate = 1/4 Hard Decision Data EN = 0 Big-Endian Mode Rate = 3/4Tcpendian Register for Endianness Manager Hard Decisions in DSP MemoryData HD1 HD0Endianintr = Tcpendian Programming RegisterInterleaver Indexes in DSP Memory Data Native Format DSP Memory FormatINTER3 INTER2 INTER1 INTER0 INTER0 INTER1 INTER2 INTER3Endianextr = Extrinsic DataExtrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 ArchitectureEXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 Sub-block and Sliding Window Segmentation MAP Unit Block DiagramExamples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Subframe Segmentation SP mode onlyReliability and Prolog Length Calculation Code Rates Added FeaturesProgramming Valid Re-Encode Symbols Used for ComparisonInput Sign Log EquationEDMA3 Parameters in Shared Processing SP Mode EDMA3 Parameters in Standalone SA ModeEDMA3 Resources 1 TCP2 Dedicated EDMA3 ResourcesInput Configuration Parameters Transfer Programming Standalone SA ModeEDMA3 Programming Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Output Parameters Transfer Input Configurations Parameters ProgrammingOpmod TCPIC0 Programming Shared-Processing SP ModeInter TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Events Generation Output ParametersInter TCPIC0 Inter = Outf Errors and Status Debug Mode Pause After Each MapErrors Error Status ERRUnexpected Memory Access ACC Unexpected Signal to Noise Ratio SNRUnexpected Frame Length F Unexpected Prolog Length PStatus 13.2.13 TCP2 Active Iteration Status Activeiter 13.2.12 TCP2 Active State Status Activestate13.2.14 TCP2 SNR Status snrexceed 13.2.15 TCP2 CRC Status CrcpassDSP Products ApplicationsRfid
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