Texas Instruments TMS320C6457 DSP manual Shared-Processing SP Mode, Parameter Termination

Page 18

Shared-Processing (SP) Mode

www.ti.com

The CRC will process one sub-block at time using the data stored from the previous sub-block. The decision bit will be used by a CRC block. After all sub-blocks have been processed, the CRC bits in the CRC block are checked and compared with the last crc_length bits of the frame. If they all match, then the CRC passes.

4.4.3Parameter Termination

The parameters min_iter and max_iter need to be set prior to decode. The decoder must execute min_iter number of iterations. This parameter can be set from 0 to 31. The decoder will stop executing when the iteration count equals max_iter. Max_iter can be set from 0 to 31 and must be equal or greater than min_iter. A zero for max is equal to 32 iterations. A zero for min is equal to 1 iteration.

4.4.3.1Maximum Iterations

Turbo decoders execute the MAP decoder twice per iteration. One execution is for non-interleaved data and the other execution is for interleaved data. This parameter sets the maximum number of decoder iterations for each block of data. Valid sizes are 0 to 31. If either the CRC passed or the SNR stopping criteria threshold has been exceeded, then the decoder will stop early. The last iteration will only process the MAP decoder for the non-interleaved data.

4.4.3.2Minimum Iterations

Turbo decoders execute the MAP decoder twice per iteration. One execution is for non-interleaved data and the other execution is for interleaved data. This parameter sets the minimum number of decoder iterations for each block of data. Valid sizes are 0 to 31 and the min_iter must be less than or equal to the max_iter. The CRC unit will not be enabled until the decoder iteration count is equal or greater than the min_iter parameter. The turbo decoder will not process the CRC, re-encode, or write to the output RAM until the minimum number of iterations has been reached.

5Shared-Processing (SP) Mode

In shared-processing (SP) mode, the DSP sends systematic and parity data, and a priori data. The TCP performs one single MAP decode and outputs extrinsic data. A priori data for MAP1 is obtained by de-interleaving the extrinsic data from the previous MAP2, and a priori data for MAP2 is obtained by interleaving the extrinsics data from the previous MAP1. An overview of the SP mode is shown in Figure 16. Note that the systematic and parity data to be sent to the TCP has to be demultiplexed from the original flow described in Section 5.1. The DSP must perform the input data demultiplexing, interleaving, deinterleaving operations, hard decision calculation, and any stopping criteria algorithm.

18

TMS320C6457 Turbo-Decoder Coprocessor 2

SPRUGK1–March 2009

Page 17 Page 19
Image 18
Page 17 Page 19
Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Related Documentation From Texas Instruments About This ManualNotational Conventions TrademarksFeatures TMS320C6457 Turbo-Decoder CoprocessorGPP and IS2000 Turbo-Encoder Block Diagram IntroductionGPP and IS2000 Turbo-Decoder Block Diagram OverviewStandalone SA Mode TCP2 ModeInput Data Format Systematic and Parity DataSP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Interleaver Indexes Output Decision Data FormatStopping Criteria Interleaver DataStopping Test Unit SNR Threshold TerminationCRC Termination Maximum Iterations Shared-Processing SP ModeParameter Termination Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Output Data Format Priori DataRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 TCP2 RAMs RegistersTCP2 Registers NameRegisters Bit Field Peripheral Identification Register PIDPeripheral Identification Register PID Field Descriptions DescriptionTCP2 Input Configuration Register 0 TCPIC0 Bit Field Value DescriptionSNR TCP2 Input Configuration Register 1 TCPIC1TCP2 Input Configuration Register 2 TCPIC2 MaxitTCP2 Input Configuration Register 3 TCPIC3 TCP2 Input Configuration Register 4 TCPIC4 CrciterpassCrclen CRC Examples TCP2 Input Configuration Register 5 TCPIC5Tail Symbols CrcpolyTCP2 Input Configuration Register 6 TCPIC6 TAIL110 TCP2 Input Configuration Register 7 TCPIC7 TAIL211 TCP2 Input Configuration Register 8 TCPIC8 TAIL312 TCP2 Input Configuration Register 9 TCPIC9 TAIL413 TCP2 Input Configuration Register 10 TCPIC10 14 TCP2 Input Configuration Register 11 TCPIC11TAIL5 TCP2 Input Configuration Register 11 TCPIC11 EXTSCALE03 15 TCP2 Input Configuration Register 12 TCPIC1216 TCP2 Input Configuration Register 13 TCPIC13 EXTSCALE4717 TCP2 Input Configuration Register 14 TCPIC14 EXTSCALE811EXTSCALE1215 18 TCP2 Input Configuration Register 15 TCPIC15Extrinsic Scale Registers Iteration NumberTCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions 19 TCP2 Output Parameter Register 0 TCPOUT020 TCP2 Output Parameter Register 1 TCPOUT1 TCP2 Output Parameter Register 1 TCPOUT1 Field DescriptionsTCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions 21 TCP2 Output Parameter Register 2 TCPOUT222 TCP2 Execution Register Tcpexe TCP2 Execution Register Tcpexe Field DescriptionsEndian Extr Intr 23 TCP2 Endian Register TcpendTCP2 Endian Register Tcpend Field Descriptions Endianextr24 TCP2 Error Register Tcperr TCP2 Error Register Tcperr Field DescriptionsSubframe length 25 TCP2 Status Register Tcpstat TCP2 Status Register Tcpstat Field DescriptionsTcpstate Waiting for RAM extrinsic memory 0 to be read Soft = 26 TCP2 Emulation Register TcpemuTCP2 Emulation Register Tcpemu Field Descriptions Soft FreeEndianness Data Memory for SystematicData Memory 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116EN = 0 Big-Endian Mode Rate = 1/4 EN = 0 Big-Endian Mode Rate = 3/4 Hard Decision DataData Hard Decisions in DSP MemoryTcpendian Register for Endianness Manager HD1 HD0Interleaver Indexes in DSP Memory Tcpendian Programming RegisterEndianintr = Data Native Format DSP Memory FormatINTER0 INTER1 INTER2 INTER3 INTER3 INTER2 INTER1 INTER0Extrinsic Data Endianextr =Extrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = Architecture EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0EXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 MAP Unit Block Diagram Sub-block and Sliding Window SegmentationSubframe Segmentation SP mode only Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and WinrelReliability and Prolog Length Calculation Added Features Code RatesInput Sign Valid Re-Encode Symbols Used for ComparisonProgramming Log EquationEDMA3 Resources EDMA3 Parameters in Standalone SA ModeEDMA3 Parameters in Shared Processing SP Mode 1 TCP2 Dedicated EDMA3 ResourcesEDMA3 Programming Programming Standalone SA ModeInput Configuration Parameters Transfer Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Input Configurations Parameters Programming Output Parameters TransferInter TCPIC0 Programming Shared-Processing SP ModeOpmod TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Output Parameters Events GenerationInter TCPIC0 Inter = Outf Errors Debug Mode Pause After Each MapErrors and Status Error Status ERRUnexpected Frame Length F Unexpected Signal to Noise Ratio SNRUnexpected Memory Access ACC Unexpected Prolog Length PStatus 13.2.14 TCP2 SNR Status snrexceed 13.2.12 TCP2 Active State Status Activestate13.2.13 TCP2 Active Iteration Status Activeiter 13.2.15 TCP2 CRC Status CrcpassProducts Applications DSPRfid
Top Page Image Contents