Texas Instruments TMS320C6457 DSP manual Endianness, Data Memory for Systematic

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Endianness

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The TCP2 is halted (or paused) after processing the ongoing frame. Any current frame processing must complete. Sync vents for the new frame will be hold until TCP_EMUSUSP is released. The TCP2 is restarted from the paused state and begins the next frame operations.

In TCP_STATE = 14, the TCP_EMUSUSP will have no effect. The TCP2 will go to the next state (TCP_STATE=0) and then the emususp will be processed.

In TCP_STATE = 0, the TCP_EMUSUSP will cause the emuack to go active if no EDMA3 transactions are active.

In TCP_STATE = 1, the TCP_EMUSUSP will cause the emuack to go active if no EDMA3 transactions are active. The memory_access error bit will not go active if emuack = 1, and the tcp_int will not trigger if the memories are accessed while emuack = 1.

The emususp_rt signal is not used in the TCP2. Bit[2](RT_SEL) for the emulation register is not included and the bit is reserved.

7Endianness

The endianness manager is responsible for managing the endianness of data when DSP is configured in big endian mode. When the DSP is configured in little-endian mode, the endianness manager has no effect.

This architecture supports both big- and little-endian operation.

The TCP2 always works in little-endian mode, the input/output data to/from the processing unit is always in little-endian format. Therefore, the role of the endianness manager is to order the data correctly when the DSP is configured in big-endian mode.

For the data represented on the configuration (CFG) data bus, byte endianness is not an issue. The endianness manager has no effect on 32-bit data on the CFG bus.

In all cases except for interleaver indexes and extrinsics, the endianness manager swaps the words within the double-word for all TCP2 incoming 64-bit data (Figure 57 and Figure 58) and all TCP2 outgoing 64-bit data (Figure 59 and Figure 60).

Figure 57. Data Source - EDMA3 (Big Endian)

63	32	31	0
	A		B

Figure 58. Data Destination - Kernel (Little Endian)

63	32	31	0
	B		A

Figure 59. Data Source - Kernel (Little Endian)

63	32	31	0
	B		A

Figure 60. Data Destination - EDMA3 (Big Endian)

63	32	31	0
	A		B

7.1Data Memory for Systematic

50	TMS320C6457 Turbo-Decoder Coprocessor 2	SPRUGK1–March 2009
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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Related Documentation From Texas Instruments About This ManualNotational Conventions TrademarksFeatures TMS320C6457 Turbo-Decoder CoprocessorGPP and IS2000 Turbo-Encoder Block Diagram IntroductionGPP and IS2000 Turbo-Decoder Block Diagram OverviewStandalone SA Mode TCP2 ModeInput Data Format Systematic and Parity DataSP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Interleaver Indexes Output Decision Data FormatStopping Criteria Interleaver DataCRC Termination Stopping Test UnitSNR Threshold Termination Maximum Iterations Shared-Processing SP ModeParameter Termination Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Rsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 Output Data FormatPriori Data TCP2 RAMs RegistersTCP2 Registers NameRegisters Bit Field Peripheral Identification Register PIDPeripheral Identification Register PID Field Descriptions DescriptionTCP2 Input Configuration Register 0 TCPIC0 Bit Field Value DescriptionSNR TCP2 Input Configuration Register 1 TCPIC1TCP2 Input Configuration Register 2 TCPIC2 MaxitTCP2 Input Configuration Register 3 TCPIC3 Crclen TCP2 Input Configuration Register 4 TCPIC4Crciterpass CRC Examples TCP2 Input Configuration Register 5 TCPIC5Tail Symbols CrcpolyTCP2 Input Configuration Register 6 TCPIC6 TAIL110 TCP2 Input Configuration Register 7 TCPIC7 TAIL211 TCP2 Input Configuration Register 8 TCPIC8 TAIL312 TCP2 Input Configuration Register 9 TCPIC9 TAIL4TAIL5 13 TCP2 Input Configuration Register 10 TCPIC1014 TCP2 Input Configuration Register 11 TCPIC11 TCP2 Input Configuration Register 11 TCPIC11 EXTSCALE03 15 TCP2 Input Configuration Register 12 TCPIC1216 TCP2 Input Configuration Register 13 TCPIC13 EXTSCALE4717 TCP2 Input Configuration Register 14 TCPIC14 EXTSCALE811EXTSCALE1215 18 TCP2 Input Configuration Register 15 TCPIC15Extrinsic Scale Registers Iteration NumberTCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions 19 TCP2 Output Parameter Register 0 TCPOUT020 TCP2 Output Parameter Register 1 TCPOUT1 TCP2 Output Parameter Register 1 TCPOUT1 Field DescriptionsTCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions 21 TCP2 Output Parameter Register 2 TCPOUT222 TCP2 Execution Register Tcpexe TCP2 Execution Register Tcpexe Field DescriptionsEndian Extr Intr 23 TCP2 Endian Register TcpendTCP2 Endian Register Tcpend Field Descriptions Endianextr24 TCP2 Error Register Tcperr TCP2 Error Register Tcperr Field DescriptionsSubframe length Tcpstate 25 TCP2 Status Register TcpstatTCP2 Status Register Tcpstat Field Descriptions Waiting for RAM extrinsic memory 0 to be read Soft = 26 TCP2 Emulation Register TcpemuTCP2 Emulation Register Tcpemu Field Descriptions Soft FreeEndianness Data Memory for SystematicData Memory 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116EN = 0 Big-Endian Mode Rate = 1/4 EN = 0 Big-Endian Mode Rate = 3/4 Hard Decision DataData Hard Decisions in DSP MemoryTcpendian Register for Endianness Manager HD1 HD0Interleaver Indexes in DSP Memory Tcpendian Programming RegisterEndianintr = Data Native Format DSP Memory FormatINTER0 INTER1 INTER2 INTER3 INTER3 INTER2 INTER1 INTER0Extrinsic in DSP Memory Endianextr = Extrinsic DataEndianextr = Data Source Kernel Endianextr = EXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 ArchitectureEXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 MAP Unit Block Diagram Sub-block and Sliding Window SegmentationSubframe Segmentation SP mode only Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and WinrelReliability and Prolog Length Calculation Added Features Code RatesInput Sign Valid Re-Encode Symbols Used for ComparisonProgramming Log EquationEDMA3 Resources EDMA3 Parameters in Standalone SA ModeEDMA3 Parameters in Shared Processing SP Mode 1 TCP2 Dedicated EDMA3 ResourcesEDMA3 Programming Programming Standalone SA ModeInput Configuration Parameters Transfer Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Input Configurations Parameters Programming Output Parameters TransferInter TCPIC0 Programming Shared-Processing SP ModeOpmod TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Inter TCPIC0 Inter = Outf Output ParametersEvents Generation Errors Debug Mode Pause After Each MapErrors and Status Error Status ERRUnexpected Frame Length F Unexpected Signal to Noise Ratio SNRUnexpected Memory Access ACC Unexpected Prolog Length PStatus 13.2.14 TCP2 SNR Status snrexceed 13.2.12 TCP2 Active State Status Activestate13.2.13 TCP2 Active Iteration Status Activeiter 13.2.15 TCP2 CRC Status CrcpassRfid Products ApplicationsDSP