Texas Instruments TMS320C6457 DSP manual Extrinsics Transfer

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Programming

1.The EDMA3 input configuration parameters transfer parameters of the next user-channel MAP, if there is one ready to be decoded.

2.Dummy EDMA3 transfer parameters, if there are no more user channels LOG-MAP ready to be decoded.

9.3.1.4Extrinsics Transfer

This EDMA3 transfer to the extrinsics buffer is a TCPREVT frame-synchronized transfer. The parameters should be set as:

∙OPTIONS:

–ITCCEN = 0 (Intermediate transfer complete chaining is disabled)

–TCCEN = 0 (Transfer complete chaining is disabled)

–ITCINTEN = 0 (Intermediate transfer complete interrupt is disabled)

–TCINTEN = 1 (Transfer complete interrupt is disabled)

–TCC = 1 to 63 (Transfer Complete Code)

–TCCMODE = 0 (Normal Completion)

–FWID = Don't care

–STAT = 0 (Entry is updated as normal)

–SYNCDIM = 0 (A-Sync. Each event triggers the transfer of ACNT elements.)

–DAM = 0 (Dst addressing within an array increments. Dst is not a FIFO.)

–SAM = 0 (Src addressing within an array increments. Source is not a FIFO.)

∙If the OPMODE == FIRST_SUB_FRAME SOURCE ADDRESS: TCPEXT (5003 0000h)

∙If the OPMODE == MIDDLE_SUB_FRAME or LAST_SUB_FRAME SOURCE ADDRESS: TCPEXT (5003 0000h + prolog_length)

∙ACNT = 8 * ceil ((frame_length)/8) ⇒ (No of bytes in an array)

∙BCNT = 1 (No of arrays of length ACNT)

∙DESTINATION ADDRESS: User extrinsics start address (must be double-word aligned)

∙SRCBIDX = 0 (Source 2nd Dimension Index)

∙DSTBIDX = 0 (Destination 2nd Dimension Index)

∙SRCCIDX = 0 (Source 3rd Dimension Index)

∙DSTCIDX = 0 (Destination 3rd Dimension Index)

∙CCNT = 1 (No of frames in a block)

∙BCNTRLD: Don't care

∙LINK ADDRESS: See cases 1 and 2 below

Upon completion, this EDMA3 transfer is linked to one of the following:

1.The EDMA3 extrinsics transfer parameters of the next user-channel, if there is one ready to be decoded.

2.Null EDMA3 transfer parameters (all with all zeros), if there are no more user-channels ready to be decoded.

9.3.2Input Configurations Parameters Programming

The frame length (FL bits in TCPIC0) should be set to the total shared-processing frame length (prior to turbo-encoding and not including any tail information).

The maximum number of iterations (MAXIT bits in TCPIC2) should be selected as a function of the overall system performance. A value of 0 sets the maximum number of iterations to its maximum (32).

∙The SNR threshold ratio (SNR bits in TCPIC2) should be disabled.

∙The CRC bits in (TCPIC4) should be disabled.

∙The prolog reduction should be disabled.

∙The extrinsic scaling should be disabled.

SPRUGK1–March 2009

TMS320C6457 Turbo-Decoder Coprocessor 2

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments TrademarksTMS320C6457 Turbo-Decoder Coprocessor FeaturesIntroduction GPP and IS2000 Turbo-Encoder Block DiagramOverview GPP and IS2000 Turbo-Decoder Block DiagramTCP2 Mode Standalone SA ModeSystematic and Parity Data Input Data FormatSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Stopping Criteria Output Decision Data FormatInterleaver Indexes Interleaver DataSNR Threshold Termination Stopping Test UnitCRC Termination Parameter Termination Shared-Processing SP ModeMaximum Iterations Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Priori Data Output Data FormatRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 TCP2 Registers RegistersTCP2 RAMs NameRegisters Peripheral Identification Register PID Field Descriptions Peripheral Identification Register PIDBit Field DescriptionBit Field Value Description TCP2 Input Configuration Register 0 TCPIC0TCP2 Input Configuration Register 2 TCPIC2 TCP2 Input Configuration Register 1 TCPIC1SNR MaxitTCP2 Input Configuration Register 3 TCPIC3 Crciterpass TCP2 Input Configuration Register 4 TCPIC4Crclen Tail Symbols TCP2 Input Configuration Register 5 TCPIC5CRC Examples CrcpolyTAIL1 TCP2 Input Configuration Register 6 TCPIC6TAIL2 10 TCP2 Input Configuration Register 7 TCPIC7TAIL3 11 TCP2 Input Configuration Register 8 TCPIC8TAIL4 12 TCP2 Input Configuration Register 9 TCPIC914 TCP2 Input Configuration Register 11 TCPIC11 13 TCP2 Input Configuration Register 10 TCPIC10TAIL5 TCP2 Input Configuration Register 11 TCPIC11 16 TCP2 Input Configuration Register 13 TCPIC13 15 TCP2 Input Configuration Register 12 TCPIC12EXTSCALE03 EXTSCALE47EXTSCALE811 17 TCP2 Input Configuration Register 14 TCPIC14Extrinsic Scale Registers 18 TCP2 Input Configuration Register 15 TCPIC15EXTSCALE1215 Iteration Number20 TCP2 Output Parameter Register 1 TCPOUT1 19 TCP2 Output Parameter Register 0 TCPOUT0TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions22 TCP2 Execution Register Tcpexe 21 TCP2 Output Parameter Register 2 TCPOUT2TCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions TCP2 Execution Register Tcpexe Field DescriptionsTCP2 Endian Register Tcpend Field Descriptions 23 TCP2 Endian Register TcpendEndian Extr Intr EndianextrTCP2 Error Register Tcperr Field Descriptions 24 TCP2 Error Register TcperrSubframe length TCP2 Status Register Tcpstat Field Descriptions 25 TCP2 Status Register TcpstatTcpstate Waiting for RAM extrinsic memory 0 to be read TCP2 Emulation Register Tcpemu Field Descriptions 26 TCP2 Emulation Register TcpemuSoft = Soft FreeData Memory for Systematic Endianness6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 Data MemoryEN = 0 Big-Endian Mode Rate = 1/4 Hard Decision Data EN = 0 Big-Endian Mode Rate = 3/4Tcpendian Register for Endianness Manager Hard Decisions in DSP MemoryData HD1 HD0Endianintr = Tcpendian Programming RegisterInterleaver Indexes in DSP Memory Data Native Format DSP Memory FormatINTER3 INTER2 INTER1 INTER0 INTER0 INTER1 INTER2 INTER3Endianextr = Extrinsic DataExtrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 ArchitectureEXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 Sub-block and Sliding Window Segmentation MAP Unit Block DiagramExamples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Subframe Segmentation SP mode onlyReliability and Prolog Length Calculation Code Rates Added FeaturesProgramming Valid Re-Encode Symbols Used for ComparisonInput Sign Log EquationEDMA3 Parameters in Shared Processing SP Mode EDMA3 Parameters in Standalone SA ModeEDMA3 Resources 1 TCP2 Dedicated EDMA3 ResourcesInput Configuration Parameters Transfer Programming Standalone SA ModeEDMA3 Programming Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Output Parameters Transfer Input Configurations Parameters ProgrammingOpmod TCPIC0 Programming Shared-Processing SP ModeInter TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Events Generation Output ParametersInter TCPIC0 Inter = Outf Errors and Status Debug Mode Pause After Each MapErrors Error Status ERRUnexpected Memory Access ACC Unexpected Signal to Noise Ratio SNRUnexpected Frame Length F Unexpected Prolog Length PStatus 13.2.13 TCP2 Active Iteration Status Activeiter 13.2.12 TCP2 Active State Status Activestate13.2.14 TCP2 SNR Status snrexceed 13.2.15 TCP2 CRC Status CrcpassDSP Products ApplicationsRfid
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