Texas Instruments TMS320C6457 DSP manual Shared-Processing SP Mode Block Diagram

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Shared-Processing (SP) Mode

Figure 16. Shared-Processing (SP) Mode Block Diagram

A for MAP 1 and A’ for MAP2

B for MAP1 and B’ for MAP2 (only rate 1/4)

X for MAP1 or X’ for MAP2

EXT1: extrinsics after MAP1

EXT2: extrinsics after MAP2

MAP

decoder

unit

EXT1,2

The shared-processing mode allows the DSP/TCP2 system to support frames strictly larger than 20730. The DSP breaks the large frame into 2 or more smaller frames of 20480 or less. Each frame is called a subframe. The size of all the subframes (except the last subframe) must be divisible by 256. The DSP breaks the large frame into several sub-frames following the process shown below. The first subframe does not have a header section and its tail section is equal to the prolog size. The middle subframe header and tail section sizes are each equal to the prolog size. The last subframe header size is equal to the prolog size and the tail section is equal to the tail size. The prolog size must be integer divisible by 8. The sub-frames reliability portions are sequenced in order to create the full frame.

1.The first subframe (required) will have a opmode of 1. The middle subframe(s) (optional) have a opmode of 2. The last subframe (required) will have a opmode of 3.

2.The size of all the subframes (except the last subframe) must be integer divisible by 256 and Max sub frame size = 20480 = 80*256.

3.The first and middle subframes should have the same size. The last subframe should be approximately the same size as the other subframes.

4.The last subframe size must be at least 129.

SPRUGK1–March 2009

TMS320C6457 Turbo-Decoder Coprocessor 2

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Trademarks About This ManualNotational Conventions Related Documentation From Texas InstrumentsTMS320C6457 Turbo-Decoder Coprocessor FeaturesIntroduction GPP and IS2000 Turbo-Encoder Block DiagramOverview GPP and IS2000 Turbo-Decoder Block DiagramTCP2 Mode Standalone SA ModeSystematic and Parity Data Input Data FormatSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5EN = 0 Big-Endian Mode Rate = 1/4 Interleaver Data Output Decision Data FormatStopping Criteria Interleaver IndexesSNR Threshold Termination Stopping Test UnitCRC Termination Minimum Iterations Shared-Processing SP ModeParameter Termination Maximum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Priori Data Output Data FormatRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 Name RegistersTCP2 Registers TCP2 RAMsRegisters Description Peripheral Identification Register PIDPeripheral Identification Register PID Field Descriptions Bit FieldBit Field Value Description TCP2 Input Configuration Register 0 TCPIC0Maxit TCP2 Input Configuration Register 1 TCPIC1TCP2 Input Configuration Register 2 TCPIC2 SNRTCP2 Input Configuration Register 3 TCPIC3 Crciterpass TCP2 Input Configuration Register 4 TCPIC4Crclen Crcpoly TCP2 Input Configuration Register 5 TCPIC5Tail Symbols CRC ExamplesTAIL1 TCP2 Input Configuration Register 6 TCPIC6TAIL2 10 TCP2 Input Configuration Register 7 TCPIC7TAIL3 11 TCP2 Input Configuration Register 8 TCPIC8TAIL4 12 TCP2 Input Configuration Register 9 TCPIC914 TCP2 Input Configuration Register 11 TCPIC11 13 TCP2 Input Configuration Register 10 TCPIC10TAIL5 TCP2 Input Configuration Register 11 TCPIC11 EXTSCALE47 15 TCP2 Input Configuration Register 12 TCPIC1216 TCP2 Input Configuration Register 13 TCPIC13 EXTSCALE03EXTSCALE811 17 TCP2 Input Configuration Register 14 TCPIC14Iteration Number 18 TCP2 Input Configuration Register 15 TCPIC15Extrinsic Scale Registers EXTSCALE1215TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions 19 TCP2 Output Parameter Register 0 TCPOUT020 TCP2 Output Parameter Register 1 TCPOUT1 TCP2 Output Parameter Register 0 TCPOUT0 Field DescriptionsTCP2 Execution Register Tcpexe Field Descriptions 21 TCP2 Output Parameter Register 2 TCPOUT222 TCP2 Execution Register Tcpexe TCP2 Output Parameter Register 2 TCPOUT2 Field DescriptionsEndianextr 23 TCP2 Endian Register TcpendTCP2 Endian Register Tcpend Field Descriptions Endian Extr IntrTCP2 Error Register Tcperr Field Descriptions 24 TCP2 Error Register TcperrSubframe length TCP2 Status Register Tcpstat Field Descriptions 25 TCP2 Status Register TcpstatTcpstate Waiting for RAM extrinsic memory 0 to be read Soft Free 26 TCP2 Emulation Register TcpemuTCP2 Emulation Register Tcpemu Field Descriptions Soft =Data Memory for Systematic Endianness6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 Data MemoryEN = 0 Big-Endian Mode Rate = 1/4 Hard Decision Data EN = 0 Big-Endian Mode Rate = 3/4HD1 HD0 Hard Decisions in DSP MemoryTcpendian Register for Endianness Manager DataData Native Format DSP Memory Format Tcpendian Programming RegisterEndianintr = Interleaver Indexes in DSP MemoryINTER3 INTER2 INTER1 INTER0 INTER0 INTER1 INTER2 INTER3Endianextr = Extrinsic DataExtrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 ArchitectureEXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 Sub-block and Sliding Window Segmentation MAP Unit Block DiagramExamples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Subframe Segmentation SP mode onlyReliability and Prolog Length Calculation Code Rates Added FeaturesLog Equation Valid Re-Encode Symbols Used for ComparisonProgramming Input Sign1 TCP2 Dedicated EDMA3 Resources EDMA3 Parameters in Standalone SA ModeEDMA3 Parameters in Shared Processing SP Mode EDMA3 ResourcesSystematics and Parities Transfer Programming Standalone SA ModeInput Configuration Parameters Transfer EDMA3 ProgrammingInterleaver Indexes Transfer Hard-Decisions Transfer Output Parameters Transfer Input Configurations Parameters ProgrammingOutf TCPIC0 Programming Shared-Processing SP ModeOpmod TCPIC0 Inter TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Events Generation Output ParametersInter TCPIC0 Inter = Outf Error Status ERR Debug Mode Pause After Each MapErrors and Status ErrorsUnexpected Prolog Length P Unexpected Signal to Noise Ratio SNRUnexpected Memory Access ACC Unexpected Frame Length FStatus 13.2.15 TCP2 CRC Status Crcpass 13.2.12 TCP2 Active State Status Activestate13.2.13 TCP2 Active Iteration Status Activeiter 13.2.14 TCP2 SNR Status snrexceedDSP Products ApplicationsRfid