Texas Instruments TMS320C6457 DSP manual Priori Transfer

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Programming

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∙Word count = 2 * ceil (frame_length/2)

∙BCNT = (Word count /2) (No of arrays of length ACNT)

∙DESTINATION ADDRESS: TCPSP (5001 0000h)

∙SRCBIDX = 8 (Source 2nd Dimension Index)

∙DSTBIDX = 8 (Destination 2nd Dimension Index)

∙SRCCIDX = 8 (Source 3rd Dimension Index)

∙DSTCIDX = 8 (Destination 3rd Dimension Index)

∙CCNT = 8 (No of frames in a block)

∙BCNTRLD: Don't care

∙LINK ADDRESS: See cases 1 and 2 below

Upon completion, this EDMA3 transfer is linked to one of the following:

1.The EDMA3 input configuration parameters transfer parameters of the next user-channel, if there is one ready to be decoded and the current decoding is a MAP0 from the first iteration.

2.Dummy EDMA3 transfer parameters, if there are no more user channels ready to be decoded.

9.3.1.3A Priori Transfer

This EDMA3 transfer to the a priori memory is a TCPXEVT chained and frame-synchronized transfer. This EDMA3 transfer is chained from the systematic and parity data transfer and occurs only when executing any MAP but the MAP0 of the first iteration; that is, the OPMOD bits in TCPIC0 must be set to 2h, 4h, and

6h respectively. The parameters should be set as:

∙OPTIONS:

–ITCCEN = 0 (Intermediate transfer complete chaining is disabled)

–TCCEN = 0 (Transfer complete chaining is disabled)

–ITCINTEN = 0 (Intermediate transfer complete interrupt is disabled)

–TCINTEN = 1 (Transfer complete interrupt is enabled)

–TCC = 1 to 63 (Transfer Complete Code)

–TCCMODE = 0 (Normal Completion)

–FWID = Don't care

–STAT = 0 (Entry is updated as normal)

–SYNCDIM = 1 (A-Sync. Each event triggers the transfer of ACNT elements.)

–DAM = 0 (Dst addressing within an array increments. Dst is not a FIFO.)

–SAM = 0 (Src addressing within an array increments. Source is not a FIFO.)

∙SOURCE ADDRESS: A priori start address (must be double-word aligned)

∙If the OPMOD == FIRST_SUB_FRAME

ACNT = 8 * ceil ((frame_length + prolog_length)/8) ⇒ (No of bytes in an array)

∙If the OPMOD == MIDDLE_SUB_FRAME

ACNT = 8 * ceil ((frame_length + 2 * prolog_length)/8) ⇒ (No of bytes in an array)

∙If the OPMOD == LAST_SUB_FRAME

ACNT = 8 * ceil ((frame_length + prolog_length)/8) ⇒ (No of bytes in an array)

∙BCNT = 1 (No of arrays of length ACNT)

∙DESTINATION ADDRESS: TCPAP (5004 0000h)

∙SRCBIDX = 0 (Source 2nd Dimension Index)

∙DSTBIDX = 0 (Destination 2nd Dimension Index)

∙SRCCIDX = 0 (Source 3rd Dimension Index)

∙DSTCIDX = 0 (Destination 3rd Dimension Index)

∙CCNT = 1 (No of frames in a block)

∙BCNTRLD: Don't care

∙LINK ADDRESS: See cases 1 and 2 below

Upon completion, this EDMA3 transfer is linked to one of the following:

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TMS320C6457 Turbo-Decoder Coprocessor 2

SPRUGK1–March 2009

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Contents Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables About This Manual Notational ConventionsRelated Documentation From Texas Instruments TrademarksFeatures TMS320C6457 Turbo-Decoder CoprocessorGPP and IS2000 Turbo-Encoder Block Diagram IntroductionGPP and IS2000 Turbo-Decoder Block Diagram OverviewStandalone SA Mode TCP2 ModeInput Data Format Systematic and Parity DataRsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0EN = 0 Big-Endian Mode Rate = 1/4 Output Decision Data Format Stopping CriteriaInterleaver Indexes Interleaver DataStopping Test Unit SNR Threshold TerminationCRC Termination Shared-Processing SP Mode Parameter TerminationMaximum Iterations Minimum IterationsShared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Output Data Format Priori DataRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 Registers TCP2 RegistersTCP2 RAMs NameRegisters Peripheral Identification Register PID Peripheral Identification Register PID Field DescriptionsBit Field DescriptionTCP2 Input Configuration Register 0 TCPIC0 Bit Field Value DescriptionTCP2 Input Configuration Register 1 TCPIC1 TCP2 Input Configuration Register 2 TCPIC2SNR MaxitTCP2 Input Configuration Register 3 TCPIC3 TCP2 Input Configuration Register 4 TCPIC4 CrciterpassCrclen TCP2 Input Configuration Register 5 TCPIC5 Tail SymbolsCRC Examples CrcpolyTCP2 Input Configuration Register 6 TCPIC6 TAIL110 TCP2 Input Configuration Register 7 TCPIC7 TAIL211 TCP2 Input Configuration Register 8 TCPIC8 TAIL312 TCP2 Input Configuration Register 9 TCPIC9 TAIL413 TCP2 Input Configuration Register 10 TCPIC10 14 TCP2 Input Configuration Register 11 TCPIC11TAIL5 TCP2 Input Configuration Register 11 TCPIC11 15 TCP2 Input Configuration Register 12 TCPIC12 16 TCP2 Input Configuration Register 13 TCPIC13EXTSCALE03 EXTSCALE4717 TCP2 Input Configuration Register 14 TCPIC14 EXTSCALE81118 TCP2 Input Configuration Register 15 TCPIC15 Extrinsic Scale RegistersEXTSCALE1215 Iteration Number19 TCP2 Output Parameter Register 0 TCPOUT0 20 TCP2 Output Parameter Register 1 TCPOUT1TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions21 TCP2 Output Parameter Register 2 TCPOUT2 22 TCP2 Execution Register TcpexeTCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions TCP2 Execution Register Tcpexe Field Descriptions23 TCP2 Endian Register Tcpend TCP2 Endian Register Tcpend Field DescriptionsEndian Extr Intr Endianextr24 TCP2 Error Register Tcperr TCP2 Error Register Tcperr Field DescriptionsSubframe length 25 TCP2 Status Register Tcpstat TCP2 Status Register Tcpstat Field DescriptionsTcpstate Waiting for RAM extrinsic memory 0 to be read 26 TCP2 Emulation Register Tcpemu TCP2 Emulation Register Tcpemu Field DescriptionsSoft = Soft FreeEndianness Data Memory for SystematicData Memory 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116EN = 0 Big-Endian Mode Rate = 1/4 EN = 0 Big-Endian Mode Rate = 3/4 Hard Decision DataHard Decisions in DSP Memory Tcpendian Register for Endianness ManagerData HD1 HD0Tcpendian Programming Register Endianintr =Interleaver Indexes in DSP Memory Data Native Format DSP Memory FormatINTER0 INTER1 INTER2 INTER3 INTER3 INTER2 INTER1 INTER0Extrinsic Data Endianextr =Extrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = Architecture EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0EXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 MAP Unit Block Diagram Sub-block and Sliding Window SegmentationSubframe Segmentation SP mode only Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and WinrelReliability and Prolog Length Calculation Added Features Code RatesValid Re-Encode Symbols Used for Comparison ProgrammingInput Sign Log EquationEDMA3 Parameters in Standalone SA Mode EDMA3 Parameters in Shared Processing SP ModeEDMA3 Resources 1 TCP2 Dedicated EDMA3 ResourcesProgramming Standalone SA Mode Input Configuration Parameters TransferEDMA3 Programming Systematics and Parities TransferInterleaver Indexes Transfer Hard-Decisions Transfer Input Configurations Parameters Programming Output Parameters TransferProgramming Shared-Processing SP Mode Opmod TCPIC0Inter TCPIC0 Outf TCPIC0Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Output Parameters Events GenerationInter TCPIC0 Inter = Outf Debug Mode Pause After Each Map Errors and StatusErrors Error Status ERRUnexpected Signal to Noise Ratio SNR Unexpected Memory Access ACCUnexpected Frame Length F Unexpected Prolog Length PStatus 13.2.12 TCP2 Active State Status Activestate 13.2.13 TCP2 Active Iteration Status Activeiter13.2.14 TCP2 SNR Status snrexceed 13.2.15 TCP2 CRC Status CrcpassProducts Applications DSPRfid
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