Xilinx 1.8 manual Licensing the Core, Before you Begin, License Options, Simulation Only, Full

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Chapter 2

Licensing the Core

This chapter provided licensing options for the Endpoint Block Plus for PCI Express core, which you must do before using the core in your designs. The core is provided under the terms of the Xilinx LogiCORE Site License Agreement, which conforms to the terms of the SignOnce IP License standard defined by the Common License Consortium.

Before you Begin

This chapter assumes you have installed the core using either the CORE Generator IP Software Update installer or by performing a manual installation after downloading the core from the web. For additional information about installing the core, see the Block Plus for PCIe product page.

License Options

The Endpoint Block Plus for PCIe core provides two license options: a Simulation Only Evaluation license and a Full license. The Simulation Only Evaluation license is provided by default with the CORE Generator. The Full license is also free of charge, but you must register for it on the Block Plus for PCIe product page. See “Obtaining a Full License” below.

Simulation Only

The Simulation Only Evaluation license, provided by default with CORE Generator, lets you assess the core functionality with either the provided example design or alongside your own design, and demonstrates the various interfaces to the core in simulation. (Functional simulation is supported by a dynamically generated gate-level netlist.)

Full

The Full license provides full access to all core functionality both in simulation and in hardware, including:

•Gate-level functional simulation support

•Back annotated gate-level simulation support

•Full implementation support including place and route and bitstream generation

•Full functionality in the programmed device with no time outs

Endpoint Block Plus v1.8 for PCI Express

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UG343 June 27, 2008

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Contents UG343 June 27 LogiCORE IP Endpoint Block Plus v1.8 for PCI ExpressDate Version Revision Revision HistoryTable of Contents Appendix Additional Design Considerations Conventions ContentsAbout This Guide Preface About This Guide Online DocumentRecommended Design Experience IntroductionAbout the Core System RequirementsCore Additional Core ResourcesTechnical Support FeedbackFeedback DocumentIntroduction Simulation Only Licensing the CoreBefore you Begin License OptionsLicensing the Core Installing Your License FileObtaining Your License Simulation Design Overview Quickstart Example DesignOverview Quickstart Example Design 1Simulation Example Design Block DiagramOverview Implementation Design OverviewExample Design Elements 3New Project Dialog Box Generating the Core5Endpoint Block Plus Main Screen Generating the CoreRunning the Simulation Setting up for SimulationSimulating the Example Design Linux Implementing the Example DesignImplementing the Example Design WindowsDirectory Structure and File Contents Component name/doc Project directoryProject directory/component name 5Implement Directory Name Description Component name/exampledesignComponent name/implement 4Example Design Directory Name Description7Simulation Directory Name Description Implement/resultsComponent name/simulation 6Results Directory Name Description9Functional Directory Name Description Simulation/dsportSimulation/functional 8dsport Directory Name Description10Tests Directory Name Description Dual Core Example DesignSimulation/tests Dual Core Example DesignDual Core Directory Structure and File Contents 13Simulation Directory Name Description Exampledesign/dualcore11Example Design Directory Name Description 12Dual Core Directory Name Description15Implement Directory Name Description 14Functional Directory Name DescriptionDevice/Part Number Package ConstraintsUser Constraints Files Wrapper File UsageAppendix Appendix Additional Design Considerations
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