Xilinx 1.8 manual Project directory/component name, Component name/doc

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Directory Structure and File Contents

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<project directory>

The project directory contains all the CORE Generator project files.

Table 3-1:Project Directory

Name	Description

	<project_dir>

<component_name>.ngc	Top-level netlist.

<component_name>.v[hd]	Verilog or VHDL simulation model.

<component_name>.xco	CORE Generator project-specific option file; can be
	used as an input to the CORE Generator.

<component_name>_flist.txt	List of files delivered with core.

<component_name>.{veovho}	Verilog or VHDL instantiation template.

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<project directory>/<component name>

The component name directory contains the release notes readme file provided with the core, which may includes tool requirements, last-minute changes, updates, and issue resolution.

Table 3-2:Component Name Directory

Name	Description

<project_dir>/<component_name>

pcie_blk_plus_readme.txt	Release notes file.

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<component name>/doc

The doc directory contains the PDF documentation provided with the core.

Table 3-3:Doc Directory

Name	Description

<project_dir>/<component_name>/doc

pcie_blk_plus_ds551.pdf	LogiCORE IP Endpoint Block Plus for PCI Express Data
	Sheet

pcie_blk_plus_gsg343.pdf	LogiCORE IP Endpoint Block Plus for PCI Express Getting
	Started Guide

pcie_blk_plus_ug341.pdf	LogiCORE IP Endpoint Block Plus for PCI Express User
	Guide

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Endpoint Block Plus v1.8 for PCI Express

www.xilinx.com

21

UG343 June 27, 2008

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Contents UG343 June 27 LogiCORE IP Endpoint Block Plus v1.8 for PCI ExpressDate Version Revision Revision HistoryTable of Contents Appendix Additional Design Considerations Contents About This GuideConventions Preface About This Guide Online DocumentAbout the Core IntroductionSystem Requirements Recommended Design ExperienceTechnical Support Additional Core ResourcesFeedback CoreFeedback DocumentIntroduction Before you Begin Licensing the CoreLicense Options Simulation OnlyInstalling Your License File Obtaining Your LicenseLicensing the Core Quickstart Example Design OverviewSimulation Design Overview Quickstart Example Design 1Simulation Example Design Block DiagramImplementation Design Overview Example Design ElementsOverview 3New Project Dialog Box Generating the Core5Endpoint Block Plus Main Screen Generating the CoreSetting up for Simulation Simulating the Example DesignRunning the Simulation Implementing the Example Design Implementing the Example DesignWindows LinuxDirectory Structure and File Contents Project directory Project directory/component nameComponent name/doc Component name/implement Component name/exampledesign4Example Design Directory Name Description 5Implement Directory Name DescriptionComponent name/simulation Implement/results6Results Directory Name Description 7Simulation Directory Name DescriptionSimulation/functional Simulation/dsport8dsport Directory Name Description 9Functional Directory Name DescriptionSimulation/tests Dual Core Example DesignDual Core Example Design 10Tests Directory Name DescriptionDual Core Directory Structure and File Contents 11Example Design Directory Name Description Exampledesign/dualcore12Dual Core Directory Name Description 13Simulation Directory Name Description15Implement Directory Name Description 14Functional Directory Name DescriptionUser Constraints Files Package ConstraintsWrapper File Usage Device/Part NumberAppendix Appendix Additional Design Considerations