Xilinx 1.8 manual Additional Core Resources, Technical Support, Feedback, Introduction

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Chapter 1: Introduction

performance, pipelined FPGA designs using Xilinx implementation software and User Constraints Files (UCF) is recommended.

Additional Core Resources

For detailed information and updates about the core, see the following documents, available from the Block Plus for PCIe product page unless otherwise noted.

•LogiCORE IP Endpoint Block Plus for PCI Express Data Sheet

•LogiCORE IP Endpoint Block Plus for PCI Express User Guide

•LogiCORE IP Endpoint Block Plus for PCI Express Release Notes (available from the core directory after generating the core)

•Virtex-5 Integrated Endpoint Block for PCI Express Designs User Guide (UG197)

Additional information and resources related to the PCI Express technology are available from the following web sites:

•PCI Express at PCI-SIG

•PCI Express Developer’s Forum

Technical Support

For technical support, go to www.xilinx.com/support. Questions are routed to a team of engineers with expertise using the Endpoint Block Plus for PCI Express core.

Xilinx provides technical support for use of this product as described in the LogiCORE IP Endpoint Block Plus for PCI Express User Guide and the LogiCORE IP Endpoint Block Plus for PCI Express Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines.

Feedback

Xilinx welcomes comments and suggestions about the core and the accompanying documentation.

Core

For comments or suggestions about the core, please submit a WebCase from

www.xilinx.com/support. Be sure to include the following information:

•Product name

•Core version number

•Explanation of your comments

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Endpoint Block Plus v1.8 for PCI Express

 

 

UG343 June 27, 2008

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Contents LogiCORE IP Endpoint Block Plus v1.8 for PCI Express UG343 June 27Revision History Date Version RevisionTable of Contents Appendix Additional Design Considerations Conventions ContentsAbout This Guide Online Document Preface About This GuideIntroduction About the CoreSystem Requirements Recommended Design ExperienceAdditional Core Resources Technical SupportFeedback CoreDocument FeedbackIntroduction Licensing the Core Before you BeginLicense Options Simulation OnlyLicensing the Core Installing Your License FileObtaining Your License Simulation Design Overview Quickstart Example DesignOverview 1Simulation Example Design Block Diagram Quickstart Example DesignOverview Implementation Design OverviewExample Design Elements Generating the Core 3New Project Dialog BoxGenerating the Core 5Endpoint Block Plus Main ScreenRunning the Simulation Setting up for SimulationSimulating the Example Design Implementing the Example Design Implementing the Example DesignWindows LinuxDirectory Structure and File Contents Component name/doc Project directoryProject directory/component name Component name/exampledesign Component name/implement4Example Design Directory Name Description 5Implement Directory Name DescriptionImplement/results Component name/simulation6Results Directory Name Description 7Simulation Directory Name DescriptionSimulation/dsport Simulation/functional8dsport Directory Name Description 9Functional Directory Name DescriptionDual Core Example Design Simulation/testsDual Core Example Design 10Tests Directory Name DescriptionDual Core Directory Structure and File Contents Exampledesign/dualcore 11Example Design Directory Name Description12Dual Core Directory Name Description 13Simulation Directory Name Description14Functional Directory Name Description 15Implement Directory Name DescriptionPackage Constraints User Constraints FilesWrapper File Usage Device/Part NumberAppendix Appendix Additional Design Considerations
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