Xilinx 1.8 manual Simulation/dsport, Simulation/functional, 8dsport Directory Name Description

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Chapter 3: Quickstart Example Design

simulation/dsport

The dsport directory contains the data stream simulation scripts provided with the core.

Table 3-8:dsport Directory

Name	Description

<project_dir>/<component_name>/simulation/dsport

dsport_cfg.v[hd]

pci_exp_expect_tasks.v

pci_exp_1_lane_64b_dsport.v[hd] pci_exp_4_lane_64b_dsport.v[hd] pci_exp_usrapp_cfg.v[hd] pci_exp_usrapp_com.v pci_exp_usrapp_rx.v[hd] pci_exp_usrapp_tx.v[hd] xilinx_pci_exp_downstream_port.v[hd] xilinx_pci_exp_dsport.v[hd]

test_interface.vhd

Downstream port model files.

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simulation/functional

The functional directory contains functional simulation scripts provided with the core.

Table 3-9:Functional Directory

	Name	Description

	<project_dir>/<component_name>/simulation/functional

	board_rtl_x01_v4fx.f
	board_rtl_x04_v4fx.f
	board_rtl_x08_v4fx.f
	board_rtl_x01_v4fx_ncv.f	List of files for RTL simulations.
	board_rtl_x04_v4fx_ncv.f
	board_rtl_x08_v4fx_ncv.f
	board_rtl.f

	simulate_mti.do	Simulation script for ModelSim.

	simulate_ncsim.sh	Simulation script for Cadence IUS.

	simulate_vcs.sh	Simulation script for VCS.

	xilinx_lib_vcs.f	Points to the required SmartModel.
	xilinx_lib_vnc.f	Points to the required SmartModel.
	xilinx_lib_vnc.f

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24	www.xilinx.com	Endpoint Block Plus v1.8 for PCI Express
		UG343 June 27, 2008

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Contents LogiCORE IP Endpoint Block Plus v1.8 for PCI Express UG343 June 27Revision History Date Version RevisionTable of Contents Appendix Additional Design Considerations Contents About This GuideConventions Online Document Preface About This GuideIntroduction About the CoreSystem Requirements Recommended Design ExperienceAdditional Core Resources Technical SupportFeedback CoreDocument FeedbackIntroduction Licensing the Core Before you BeginLicense Options Simulation OnlyInstalling Your License File Obtaining Your LicenseLicensing the Core Quickstart Example Design OverviewSimulation Design Overview 1Simulation Example Design Block Diagram Quickstart Example DesignImplementation Design Overview Example Design ElementsOverview Generating the Core 3New Project Dialog BoxGenerating the Core 5Endpoint Block Plus Main ScreenSetting up for Simulation Simulating the Example DesignRunning the Simulation Implementing the Example Design Implementing the Example DesignWindows LinuxDirectory Structure and File Contents Project directory Project directory/component nameComponent name/doc Component name/exampledesign Component name/implement4Example Design Directory Name Description 5Implement Directory Name DescriptionImplement/results Component name/simulation6Results Directory Name Description 7Simulation Directory Name DescriptionSimulation/dsport Simulation/functional8dsport Directory Name Description 9Functional Directory Name DescriptionDual Core Example Design Simulation/testsDual Core Example Design 10Tests Directory Name DescriptionDual Core Directory Structure and File Contents Exampledesign/dualcore 11Example Design Directory Name Description12Dual Core Directory Name Description 13Simulation Directory Name Description14Functional Directory Name Description 15Implement Directory Name DescriptionPackage Constraints User Constraints FilesWrapper File Usage Device/Part NumberAppendix Appendix Additional Design Considerations