Xilinx 1.8 manual Introduction, About the Core, System Requirements, Recommended Design Experience

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Chapter 1

Introduction

The Endpoint Block Plus for PCI Express is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex™-5 FPGA devices. This core supports Verilog® and VHDL. The example design described in this guide is provided in Verilog and VHDL.

This chapter introduces the core and provides related information, including system requirements, recommended design experience, additional resources, technical support, and submitting feedback to Xilinx.

About the Core

The Endpoint Block Plus for PCIe core is a Xilinx CORE Generator™ IP core, included in the latest IP Update on the Xilinx IP Center. For additional information about the core, see the Block Plus for PCIe product page. For information about obtaining a license for the core, see Chapter 2, “Licensing the Core.”

System Requirements

Windows

•Windows XP® Professional 32-bit/64-bit

•Windows Vista® Business 32-bit/64-bit

Linux

•Red Hat® Enterprise Linux WS v4.0 32-bit/64-bit

•Red Hat® Enterprise Desktop v5.0 32-bit/64-bit (with Workstation Option)

•SUSE Linux Enterprise (SLE) v10.1 32-bit/64-bit

Software

•ISE™ 10.1

Check the release notes for the required Service Pack; ISE Service Packs can be downloaded from www.xilinx.com/support/download/index.htm.

Recommended Design Experience

Although the Endpoint Block Plus for PCIe is a fully verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application. For best results, previous experience building high

Endpoint Block Plus v1.8 for PCI Express

www.xilinx.com

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UG343 June 27, 2008

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Contents UG343 June 27 LogiCORE IP Endpoint Block Plus v1.8 for PCI ExpressDate Version Revision Revision HistoryTable of Contents Appendix Additional Design Considerations About This Guide ContentsConventions Preface About This Guide Online DocumentRecommended Design Experience IntroductionAbout the Core System RequirementsCore Additional Core ResourcesTechnical Support FeedbackFeedback DocumentIntroduction Simulation Only Licensing the CoreBefore you Begin License OptionsObtaining Your License Installing Your License FileLicensing the Core Overview Quickstart Example DesignSimulation Design Overview Quickstart Example Design 1Simulation Example Design Block DiagramExample Design Elements Implementation Design OverviewOverview 3New Project Dialog Box Generating the Core5Endpoint Block Plus Main Screen Generating the CoreSimulating the Example Design Setting up for SimulationRunning the Simulation Linux Implementing the Example DesignImplementing the Example Design WindowsDirectory Structure and File Contents Project directory/component name Project directoryComponent name/doc 5Implement Directory Name Description Component name/exampledesignComponent name/implement 4Example Design Directory Name Description7Simulation Directory Name Description Implement/resultsComponent name/simulation 6Results Directory Name Description9Functional Directory Name Description Simulation/dsportSimulation/functional 8dsport Directory Name Description10Tests Directory Name Description Dual Core Example DesignSimulation/tests Dual Core Example DesignDual Core Directory Structure and File Contents 13Simulation Directory Name Description Exampledesign/dualcore11Example Design Directory Name Description 12Dual Core Directory Name Description15Implement Directory Name Description 14Functional Directory Name DescriptionDevice/Part Number Package ConstraintsUser Constraints Files Wrapper File UsageAppendix Appendix Additional Design Considerations